High speed interconnect with channel extension

ABSTRACT

An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

FIELD

The present disclosure relates in general to the field of computer development, and more specifically, to high speed interconnects in microelectronic systems.

BACKGROUND

Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a corollary, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple cores, multiple hardware threads, and multiple logical processors present on individual integrated circuits, as well as other interfaces integrated within such processors. A processor or integrated circuit typically comprises a single physical processor die, where the processor die may include any number of cores, hardware threads, logical processors, interfaces, memory, controller hubs, etc.

As a result of the greater ability to fit more processing power in smaller packages, smaller computing devices have increased in popularity. Smartphones, tablets, ultrathin notebooks, and other user equipment have grown exponentially. However, these smaller devices are reliant on servers both for data storage and complex processing that exceeds the form factor. Consequently, the demand in the high-performance computing market (i.e. server space) has also increased. For instance, in modern servers, there is typically not only a single processor with multiple cores, but also multiple physical processors (also referred to as multiple sockets) to increase the computing power. But as the processing power grows along with the number of devices in a computing system, the communication between sockets and other devices becomes more critical.

Signal repeaters and re-driver circuits can be implemented in some systems to compensate for limits on physical channel length. For instance, devices may have a limited drive capability, limiting the distance that signals may be safely driven. Further, some interconnect standards can specify a limit to the physical length of a signal line. A long distance line may be divided into two or more segments, with a buffer or repeater between segments. Repeaters can include retimers and redrivers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a simplified block diagram of a system including a serial point-to-point interconnect to connect I/O devices in a computer system in accordance with one embodiment;

FIG. 2 illustrates a simplified block diagram of a layered protocol stack in accordance with one embodiment;

FIG. 3 illustrates an embodiment of a transaction descriptor.

FIG. 4 illustrates an embodiment of a serial point-to-point link.

FIG. 5 illustrates embodiments of potential High Performance Interconnect (UPI) system configurations.

FIG. 6 illustrates an embodiment of a layered protocol stack associated with UPI.

FIG. 7 illustrates a representation of an example state machine.

FIGS. 8A-8B illustrate representations of example electrical ordered sets.

FIG. 9 illustrates example control supersequences.

FIGS. 10A-10B illustrate representations of an example flit sent over example links.

FIGS. 11A-B illustrate an example multiplexer.

FIGS. 12A-B illustrate a simplified block diagrams representing example adaptation of a link.

FIG. 13 illustrates a simplified block diagram of a link including an repeater device.

FIG. 14 is a flowchart illustrating an example techniques associated with initialization and training of a link.

FIG. 15 illustrates an embodiment of a block diagram for a computing system including a multicore processor.

FIG. 16 illustrates another embodiment of a block diagram for a computing system including a multicore processor.

FIG. 17 illustrates an embodiment of a block for a computing system including multiple processor sockets.

Like reference numbers and designations in the various drawings indicate like elements.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific processor pipeline stages, specific interconnect layers, specific packet/transaction configurations, specific transaction names, specific protocol exchanges, specific link widths, specific implementations, and operation etc. in order to provide a thorough understanding of the present disclosure. It may be apparent, however, to one skilled in the art that these specific details need not necessarily be employed to practice the subject matter of the present disclosure. In other instances, well detailed description of known components or methods has been avoided, such as specific and alternative processor architectures, specific logic circuits/code for described algorithms, specific firmware code, low-level interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific power down and gating techniques/logic and other specific operational details of computer system in order to avoid unnecessarily obscuring the present disclosure.

Although the following embodiments may be described with reference to energy conservation, energy efficiency, processing efficiency, and so on in specific integrated circuits, such as in computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from such features. For example, the disclosed embodiments are not limited to server computer system, desktop computer systems, laptops, Ultrabooks™, but may be also used in other devices, such as handheld devices, smartphones, tablets, other thin notebooks, systems on a chip (SOC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Here, similar techniques for a high-performance interconnect may be applied to increase performance (or even save power) in a low power interconnect. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPC), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations taught below. Moreover, the apparatus', methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimizations for energy conservation and efficiency. As may become readily apparent in the description below, the embodiments of methods, apparatus', and systems described herein (whether in reference to hardware, firmware, software, or a combination thereof) may be considered vital to a “green technology” future balanced with performance considerations.

As computing systems are advancing, the components therein are becoming more complex. The interconnect architecture to couple and communicate between the components has also increased in complexity to ensure bandwidth demand is met for optimal component operation. Furthermore, different market segments demand different aspects of interconnect architectures to suit the respective market. For example, servers require higher performance, while the mobile ecosystem is sometimes able to sacrifice overall performance for power savings. Yet, it is a singular purpose of most fabrics to provide highest possible performance with maximum power saving. Further, a variety of different interconnects can potentially benefit from subject matter described herein.

The Peripheral Component Interconnect (PCI) Express (PCIe) interconnect fabric architecture and QuickPath Interconnect (QPI) fabric architecture, among other examples, can potentially be improved according to one or more principles described herein, among other examples. For instance, a primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, and Error Handling are among some of the advanced features supported by PCI Express. Although the primary discussion herein is in reference to a new high-performance interconnect (UPI) architecture, aspects of the disclosure described herein may be applied to other interconnect architectures, such as a PCIe-compliant architecture, a QPI-compliant architecture, a MIPI compliant architecture, a high-performance architecture, or other known interconnect architecture.

Referring to FIG. 1, an embodiment of a fabric composed of point-to-point Links that interconnect a set of components is illustrated. The fabric and components of the system 100 used to implement the fabric may possess the logic and component (e.g., hardware and/or software-based) to implement one or more of the features discussed herein. System 100 includes processor 105 and system memory 110 coupled to controller hub 115. Processor 105 can include any processing element, such as a microprocessor, a host processor, an embedded processor, a co-processor, or other processor. Processor 105 is coupled to controller hub 115 through front-side bus (FSB) 106. In one embodiment, FSB 106 is a serial point-to-point interconnect as described below. In another embodiment, link 106 includes a serial, differential interconnect architecture that is compliant with different interconnect standard. One or more components of the system 100 can be provided with logic to implement the features described herein.

System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 100. System memory 110 is coupled to controller hub 115 through memory interface 116. Examples of a memory interface include a double-data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic RAM (DRAM) memory interface.

In one embodiment, controller hub 115 can include a root hub, root complex, or root controller, such as in a PCIe interconnection hierarchy. Examples of controller hub 115 include a chipset, a memory controller hub (MCH), a northbridge, an interconnect controller hub (ICH) a southbridge, and a root controller/hub. Often the term chipset refers to two physically separate controller hubs, e.g., a memory controller hub (MCH) coupled to an interconnect controller hub (ICH). Note that current systems often include the MCH integrated with processor 105, while controller 115 is to communicate with I/O devices, in a similar manner as described below. In some embodiments, peer-to-peer routing is optionally supported through root complex 115.

Here, controller hub 115 is coupled to switch/bridge 120 through serial link 119. Input/output modules 117 and 121, which may also be referred to as interfaces/ports 117 and 121, can include/implement a layered protocol stack to provide communication between controller hub 115 and switch 120. In one embodiment, multiple devices are capable of being coupled to switch 120.

Switch/bridge 120 routes packets/messages from device 125 upstream, i.e. up a hierarchy towards a root complex, to controller hub 115 and downstream, i.e. down a hierarchy away from a root controller, from processor 105 or system memory 110 to device 125. Switch 120, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices. Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I/O device, a Network Interface Controller (NIC), an add-in card, an audio processor, a network processor, a hard-drive, a storage device, a CD/DVD ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a Firewire device, a Universal Serial Bus (USB) device, a scanner, and other input/output devices. Often in the PCIe vernacular, such as device, is referred to as an endpoint. Although not specifically shown, device 125 may include a bridge (e.g., a PCIe to PCI/PCI-X bridge) to support legacy or other versions of devices or interconnect fabrics supported by such devices.

Graphics accelerator 130 can also be coupled to controller hub 115 through serial link 132. In one embodiment, graphics accelerator 130 is coupled to an MCH, which is coupled to an ICH. Switch 120, and accordingly I/O device 125, is then coupled to the ICH. I/O modules 131 and 118 are also to implement a layered protocol stack to communicate between graphics accelerator 130 and controller hub 115. Similar to the MCH discussion above, a graphics controller or the graphics accelerator 130 itself may be integrated in processor 105.

Turning to FIG. 2 an embodiment of a layered protocol stack is illustrated. Layered protocol stack 200 can includes any form of a layered communication stack, such as a QPI stack, a PCIe stack, a next generation high performance computing interconnect (UPI) stack, or other layered stack. In one embodiment, protocol stack 200 can include transaction layer 205, link layer 210, and physical layer 220. An interface, such as interfaces 117, 118, 121, 122, 126, and 131 in FIG. 1, may be represented as communication protocol stack 200. Representation as a communication protocol stack may also be referred to as a module or interface implementing/including a protocol stack.

Packets can be used to communicate information between components. Packets can be formed in the Transaction Layer 205 and Data Link Layer 210 to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information used to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their Physical Layer 220 representation to the Data Link Layer 210 representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer 205 of the receiving device.

In one embodiment, transaction layer 205 can provide an interface between a device's processing core and the interconnect architecture, such as Data Link Layer 210 and Physical Layer 220. In this regard, a primary responsibility of the transaction layer 205 can include the assembly and disassembly of packets (i.e., transaction layer packets, or TLPs). The translation layer 205 can also manage credit-based flow control for TLPs. In some implementations, split transactions can be utilized, i.e., transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response, among other examples.

Credit-based flow control can be used to realize virtual channels and networks utilizing the interconnect fabric. In one example, a device can advertise an initial amount of credits for each of the receive buffers in Transaction Layer 205. An external device at the opposite end of the link, such as controller hub 115 in FIG. 1, can count the number of credits consumed by each TLP. A transaction may be transmitted if the transaction does not exceed a credit limit. Upon receiving a response an amount of credit is restored. One example of an advantage of such a credit scheme is that the latency of credit return does not affect performance, provided that the credit limit is not encountered, among other potential advantages.

In one embodiment, four transaction address spaces can include a configuration address space, a memory address space, an input/output address space, and a message address space. Memory space transactions include one or more of read requests and write requests to transfer data to/from a memory-mapped location. In one embodiment, memory space transactions are capable of using two different address formats, e.g., a short address format, such as a 32-bit address, or a long address format, such as 64-bit address. Configuration space transactions can be used to access configuration space of various devices connected to the interconnect. Transactions to the configuration space can include read requests and write requests. Message space transactions (or, simply messages) can also be defined to support in-band communication between interconnect agents. Therefore, in one example embodiment, transaction layer 205 can assemble packet header/payload 206.

Quickly referring to FIG. 3, an example embodiment of a transaction layer packet descriptor is illustrated. In one embodiment, transaction descriptor 300 can be a mechanism for carrying transaction information. In this regard, transaction descriptor 300 supports identification of transactions in a system. Other potential uses include tracking modifications of default transaction ordering and association of transaction with channels. For instance, transaction descriptor 300 can include global identifier field 302, attributes field 304 and channel identifier field 306. In the illustrated example, global identifier field 302 is depicted comprising local transaction identifier field 308 and source identifier field 310. In one embodiment, global transaction identifier 302 is unique for all outstanding requests.

According to one implementation, local transaction identifier field 308 is a field generated by a requesting agent, and can be unique for all outstanding requests that require a completion for that requesting agent. Furthermore, in this example, source identifier 310 uniquely identifies the requestor agent within an interconnect hierarchy. Accordingly, together with source ID 310, local transaction identifier 308 field provides global identification of a transaction within a hierarchy domain.

Attributes field 304 specifies characteristics and relationships of the transaction. In this regard, attributes field 304 is potentially used to provide additional information that allows modification of the default handling of transactions. In one embodiment, attributes field 304 includes priority field 312, reserved field 314, ordering field 316, and no-snoop field 318. Here, priority sub-field 312 may be modified by an initiator to assign a priority to the transaction. Reserved attribute field 314 is left reserved for future, or vendor-defined usage. Possible usage models using priority or security attributes may be implemented using the reserved attribute field.

In this example, ordering attribute field 316 is used to supply optional information conveying the type of ordering that may modify default ordering rules. According to one example implementation, an ordering attribute of “0” denotes default ordering rules are to apply, wherein an ordering attribute of “1” denotes relaxed ordering, wherein writes can pass writes in the same direction, and read completions can pass writes in the same direction. Snoop attribute field 318 is utilized to determine if transactions are snooped. As shown, channel ID Field 306 identifies a channel that a transaction is associated with.

Returning to the discussion of FIG. 2, a Link layer 210, also referred to as data link layer 210, can act as an intermediate stage between transaction layer 205 and the physical layer 220. In one embodiment, a responsibility of the data link layer 210 is providing a reliable mechanism for exchanging Transaction Layer Packets (TLPs) between two components on a link. One side of the Data Link Layer 210 accepts TLPs assembled by the Transaction Layer 205, applies packet sequence identifier 211, i.e. an identification number or packet number, calculates and applies an error detection code, i.e. CRC 212, and submits the modified TLPs to the Physical Layer 220 for transmission across a physical to an external device.

In one example, physical layer 220 includes logical sub block 221 and electrical sub-block 222 to physically transmit a packet to an external device. Here, logical sub-block 221 is responsible for the “digital” functions of Physical Layer 221. In this regard, the logical sub-block can include a transmit section to prepare outgoing information for transmission by physical sub-block 222, and a receiver section to identify and prepare received information before passing it to the Link Layer 210.

Physical block 222 includes a transmitter and a receiver. The transmitter is supplied by logical sub-block 221 with symbols, which the transmitter serializes and transmits onto to an external device. The receiver is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to logical sub-block 221. In one example embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames 223. In addition, in one example, the receiver also provides a symbol clock recovered from the incoming serial stream.

As stated above, although transaction layer 205, link layer 210, and physical layer 220 are discussed in reference to a specific embodiment of a protocol stack (such as a PCIe protocol stack), a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented and adopt features discussed herein. As an example, a port/interface that is represented as a layered protocol can include: (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a high performance interconnect layered protocol, as described herein, is utilized.

Referring next to FIG. 4, an example embodiment of a serial point to point fabric is illustrated. A serial point-to-point link can include any transmission path for transmitting serial data. In the embodiment shown, a link can include two, low-voltage, differentially driven signal pairs: a transmit pair 406/411 and a receive pair 412/407. Accordingly, device 405 includes transmission logic 406 to transmit data to device 410 and receiving logic 407 to receive data from device 410. In other words, two transmitting paths, i.e. paths 416 and 417, and two receiving paths, i.e. paths 418 and 419, are included in some implementations of a link.

A transmission path refers to any path for transmitting data, such as a transmission line, a copper line, an optical line, a wireless communication channel, an infrared communication link, or other communication path. A connection between two devices, such as device 405 and device 410, is referred to as a link, such as link 415. A link may support one lane—each lane representing a set of differential signal pairs (one pair for transmission, one pair for reception). To scale bandwidth, a link may aggregate multiple lanes denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

A differential pair can refer to two transmission paths, such as lines 416 and 417, to transmit differential signals. As an example, when line 416 toggles from a low voltage level to a high voltage level, i.e. a rising edge, line 417 drives from a high logic level to a low logic level, i.e. a falling edge. Differential signals potentially demonstrate better electrical characteristics, such as better signal integrity, i.e. cross-coupling, voltage overshoot/undershoot, ringing, among other example advantages. This allows for a better timing window, which enables faster transmission frequencies.

In one embodiment, a high performance interconnect such as UPI can be provided. UPI can include a next-generation cache-coherent, link-based interconnect. As one example, UPI may be utilized in high performance computing platforms, such as workstations or servers, including in systems where PCIe or another interconnect protocol is typically used to connect processors, accelerators, I/O devices, and the like. However, UPI is not so limited. Instead, UPI may be utilized in any of the systems or platforms described herein. Furthermore, the individual ideas developed may be applied to other interconnects and platforms, such as PCIe, MIPI, QPI, etc.

To support multiple devices, in one example implementation, UPI can include an Instruction Set Architecture (ISA) agnostic (i.e. UPI is able to be implemented in multiple different devices). In another scenario, UPI may also be utilized to connect high performance I/O devices, not just processors or accelerators. For example, a high performance PCIe device may be coupled to UPI through an appropriate translation bridge (i.e. UPI to PCIe). Moreover, the UPI links may be utilized by many UPI based devices, such as processors, in various ways (e.g. stars, rings, meshes, etc.). FIG. 5 illustrates example implementations of multiple potential multi-socket configurations. A two-socket configuration 505, as depicted, can include two UPI links; however, in other implementations, one UPI link may be utilized. For larger topologies, any configuration may be utilized as long as an identifier (ID) is assignable and there is some form of virtual path, among other additional or substitute features. As shown, in one example, a four socket configuration 510 has an UPI link from each processor to another. But in the eight socket implementation shown in configuration 515, not every socket is directly connected to each other through an UPI link. However, if a virtual path or channel exists between the processors, the configuration is supported. A range of supported processors includes 2-32 in a native domain. Higher numbers of processors may be reached through use of multiple domains or other interconnects between node controllers, among other examples.

The UPI architecture includes a definition of a layered protocol architecture, including in some examples, protocol layers (coherent, non-coherent, and, optionally, other memory based protocols), a routing layer, a link layer, and a physical layer. Furthermore, UPI can further include enhancements related to power managers (such as power control units (PCUs)), design for test and debug (DFT), fault handling, registers, security, among other examples. FIG. 5 illustrates an embodiment of an example UPI layered protocol stack. In some implementations, at least some of the layers illustrated in FIG. 5 may be optional. Each layer deals with its own level of granularity or quantum of information (the protocol layer 605 a,b with packets 630, link layer 610 a,b with flits 635, and physical layer 605 a,b with phits 640). Note that a packet, in some embodiments, may include partial flits, a single flit, or multiple flits based on the implementation.

As a first example, a width of a phit 640 includes a 1 to 1 mapping of link width to bits (e.g. 20 bit link width includes a phit of 20 bits, etc.). Flits may have a greater size, such as 184, 192, or 200 bits. Note that if phit 640 is 20 bits wide and the size of flit 635 is 184 bits then it takes a fractional number of phits 640 to transmit one flit 635 (e.g. 9.2 phits at 20 bits to transmit an 184 bit flit 635 or 9.6 at 20 bits to transmit a 192 bit flit, among other examples). Note that widths of the fundamental link at the physical layer may vary. For example, the number of lanes per direction may include 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, etc. In one embodiment, link layer 610 a,b is capable of embedding multiple pieces of different transactions in a single flit, and one or multiple headers (e.g. 1, 2, 3, 4) may be embedded within the flit. In one example, UPI splits the headers into corresponding slots to enable multiple messages in the flit destined for different nodes.

Physical layer 605 a,b, in one embodiment, can be responsible for the fast transfer of information on the physical medium (electrical or optical etc.). The physical link can be point-to-point between two Link layer entities, such as layer 605 a and 605 b. The Link layer 610 a,b can abstract the Physical layer 605 a,b from the upper layers and provides the capability to reliably transfer data (as well as requests) and manage flow control between two directly connected entities. The Link Layer can also be responsible for virtualizing the physical channel into multiple virtual channels and message classes. The Protocol layer 620 a,b relies on the Link layer 610 a,b to map protocol messages into the appropriate message classes and virtual channels before handing them to the Physical layer 605 a,b for transfer across the physical links. Link layer 610 a,b may support multiple messages, such as a request, snoop, response, writeback, non-coherent data, among other examples.

The Physical layer 605 a,b (or PHY) of UPI can be implemented above the electrical layer (i.e. electrical conductors connecting two components) and below the link layer 610 a,b, as illustrated in FIG. 6. The Physical layer and corresponding logic can reside on each agent and connects the link layers on two agents (A and B) separated from each other (e.g. on devices on either side of a link). The local and remote electrical layers are connected by physical media (e.g. wires, conductors, optical, etc.). The Physical layer 605 a,b, in one embodiment, has two major phases, initialization and operation. During initialization, the connection is opaque to the link layer and signaling may involve a combination of timed states and handshake events. During operation, the connection is transparent to the link layer and signaling is at a speed, with all lanes operating together as a single link. During the operation phase, the Physical layer transports flits from agent A to agent B and from agent B to agent A. The connection is also referred to as a link and abstracts some physical aspects including media, width and speed from the link layers while exchanging flits and control/status of current configuration (e.g. width) with the link layer. The initialization phase includes minor phases e.g. Polling, Configuration. The operation phase also includes minor phases (e.g. link power management states).

In one embodiment, Link layer 610 a,b can be implemented so as to provide reliable data transfer between two protocol or routing entities. The Link layer can abstract Physical layer 605 a,b from the Protocol layer 620 a,b, and can be responsible for the flow control between two protocol agents (A, B), and provide virtual channel services to the Protocol layer (Message Classes) and Routing layer (Virtual Networks). The interface between the Protocol layer 620 a,b and the Link Layer 610 a,b can typically be at the packet level. In one embodiment, the smallest transfer unit at the Link Layer is referred to as a flit which a specified number of bits, such as 192 bits or some other denomination. The Link Layer 610 a,b relies on the Physical layer 605 a,b to frame the Physical layer's 605 a,b unit of transfer (phit) into the Link Layer's 610 a,b unit of transfer (flit). In addition, the Link Layer 610 a,b may be logically broken into two parts, a sender and a receiver. A sender/receiver pair on one entity may be connected to a receiver/sender pair on another entity. Flow Control is often performed on both a flit and a packet basis. Error detection and correction is also potentially performed on a flit level basis.

In one embodiment, Routing layer 615 a,b can provide a flexible and distributed method to route UPI transactions from a source to a destination. The scheme is flexible since routing algorithms for multiple topologies may be specified through programmable routing tables at each router (the programming in one embodiment is performed by firmware, software, or a combination thereof). The routing functionality may be distributed; the routing may be done through a series of routing steps, with each routing step being defined through a lookup of a table at either the source, intermediate, or destination routers. The lookup at a source may be used to inject a UPI packet into the UPI fabric. The lookup at an intermediate router may be used to route an UPI packet from an input port to an output port. The lookup at a destination port may be used to target the destination UPI protocol agent. Note that the Routing layer, in some implementations, can be thin since the routing tables, and, hence the routing algorithms, are not specifically defined by specification. This allows for flexibility and a variety of usage models, including flexible platform architectural topologies to be defined by the system implementation. The Routing layer 615 a,b relies on the Link layer 610 a,b for providing the use of up to three (or more) virtual networks (VNs)—in one example, two deadlock-free VNs, VN0 and VN1 with several message classes defined in each virtual network. A shared adaptive virtual network (VNA) may be defined in the Link layer, but this adaptive network may not be exposed directly in routing concepts, since each message class and virtual network may have dedicated resources and guaranteed forward progress, among other features and examples.

In one embodiment, UPI can include a Coherence Protocol layer 620 a,b to support agents caching lines of data from memory. An agent wishing to cache memory data may use the coherence protocol to read the line of data to load into its cache. An agent wishing to modify a line of data in its cache may use the coherence protocol to acquire ownership of the line before modifying the data. After modifying a line, an agent may follow protocol requirements of keeping it in its cache until it either writes the line back to memory or includes the line in a response to an external request. Lastly, an agent may fulfill external requests to invalidate a line in its cache. The protocol ensures coherency of the data by dictating the rules all caching agents may follow. It also provides the means for agents without caches to coherently read and write memory data.

Two conditions may be enforced to support transactions utilizing the UPI Coherence Protocol. First, the protocol can maintain data consistency, as an example, on a per-address basis, among data in agents' caches and between those data and the data in memory. Informally, data consistency may refer to each valid line of data in an agent's cache representing a most up-to-date value of the data and data transmitted in a coherence protocol packet can represent the most up-to-date value of the data at the time it was sent. When no valid copy of the data exists in caches or in transmission, the protocol may ensure the most up-to-date value of the data resides in memory. Second, the protocol can provide well-defined commitment points for requests. Commitment points for reads may indicate when the data is usable; and for writes they may indicate when the written data is globally observable and will be loaded by subsequent reads. The protocol may support these commitment points for both cacheable and uncacheable (UC) requests in the coherent memory space.

In some implementations, UPI can utilize an embedded clock. A clock signal can be embedded in data transmitted using the interconnect. With the clock signal embedded in the data, distinct and dedicated clock lanes can be omitted. This can be useful, for instance, as it can allow more pins of a device to be dedicated to data transfer, particularly in systems where space for pins is at a premium.

Physical Layer

A link can be established between two agents on either side of an interconnect. An agent sending data can be a local agent and the agent receiving the data can be a remote agent. State machines can be employed by both agents to manage various aspects of the link. In one embodiment, the Physical layer datapath can transmit flits from the link layer to the electrical front-end. The control path, in one implementation, includes a state machine (also referred to as a link training state machine or the similar). The state machine's actions and exits from states may depend on internal signals, timers, external signals or other information. In fact, some of the states, such as a few initialization states, may have timers to provide a timeout value to exit a state. Note that detect, in some embodiments, refers to detecting an event on both legs of a lane; but not necessarily simultaneously. However, in other embodiments, detect refers to detection of an event by an agent of reference. Debounce, as one example, refers to sustained assertion of a signal. In one embodiment, UPI supports operation in the event of non-function lanes. Here, lanes may be dropped at specific states.

States defined in the state machine can include reset states, initialization states, and operational states, among other categories and subcategories. In one example, some initialization states can have a secondary timer which is used to exit the state on a timeout (essentially an abort due to failure to make progress in the state). An abort may include updating of registers, such as status register. Some states can also have primary timer(s) which are used to time the primary functions in the state. Other states can be defined such that internal or external signals (such as handshake protocols) drive transition from the state to another state, among other examples.

A state machine may also support debug through single step, freeze on initialization abort and use of testers. Here, state exits can be postponed/held until the debug software is ready. In some instance, the exit can be postponed/held until the secondary timeout. Actions and exits, in one embodiment, can be based on exchange of training sequences. In one embodiment, the link state machine is to run in the local agent clock domain and transition from one state to the next is to coincide with a transmitter training sequence boundary. Status registers may be utilized to reflect the current state.

FIG. 7 illustrates a representation of at least a portion of a state machine used by agents in one example implementation of UPI. It should be appreciated that the states included in the state table of FIG. 7 include a non-exhaustive listing of possible states. For instance, some transitions are omitted to simplify the diagram. Also, some states may be combined, split, or omitted, while others might be added. Such states can include:

Event reset state: entered on a warm or cold reset event. Restores default values. Initialize counters (e.g., sync counters). May exit to another state, such as another reset state.

Timed reset state: timed state for in-band reset. May drive a predefined electrical ordered set (EOS) so remote receivers are capable of detecting the EOS and entering the timed reset as well. Receiver has lanes holding electrical settings. May exit to an agent to calibrate reset state.

Calibrate reset state: calibration without signaling on the lane (e.g. receiver calibration state) or turning drivers off. May be a predetermined amount of time in the state based on a timer. May set an operational speed. May act as a wait state when a port is not enabled. May include minimum residency time. Receiver conditioning or staggering off may occur based on design. May exit to a receiver detect state after a timeout and/or completion of calibration.

Receiver detect state: detect presence of a receiver on lane(s). May look for receiver termination (e.g., receiver pulldown insertion). May exit to calibrate reset state upon a specified value being set or when another specified value is not set. May exit to transmitter calibrate state if a receiver is detected or a timeout is reached.

Transmitter calibrate state: for transmitter calibrations. May be a timed state allocated for transmitter calibrations. May include signaling on a lane. May continuously drive an EOS, such as an electric idle exit ordered set (or EIEIOS). May exit to compliance state when done calibrating or on expiration of a timer. May exit to transmitter detect state if a counter has expired or a secondary timeout has occurred.

Transmitter detect state: qualifies valid signaling. May be a handshake state where an agent completes actions and exits to a next state based on remote agent signaling. Receiver may qualify valid signaling from transmitter. Receiver, in one embodiment, looks for a wake detect, and if debounced on one or more lanes looks for it on the other lanes. Transmitter drives a detect signal. May exit to a polling state in response to debounce being completed for all lanes and/or a timeout or if debounce on all lanes is not complete and there is a timeout. Here, one or more monitor lanes may be kept awake to debounce a wake signal. And if debounced then the other lanes are potentially debounced. This can enable power savings in low power states.

Beacon (L1b) state: provides a temporary state in which an agent may wait for the presence of a remote agent in the transmitter detect state. This state may be provided to account for instances where a repeater device (e.g., a retimer, redriver, or other repeater) is connected on a link prior to a remote endpoint also being connected to the link (with the repeater positioned between the two endpoints). A timeout condition may be observed during the transmitter detect state if no transmissions are received from another device. This would be expected if only a repeater were connected on the device as it would not generate the signals (e.g., a wake detect pattern) expected in the transmitter detect state. After a duration in which no detect pattern is received in the transmitter detect state, the agent may transition to the beacon state (L1b), in which everything is powered down for this link except wake detection circuitry (e.g., on one or more lanes). The agent may reside temporarily in the L1b state and then re-enter the transmitter detect state to determine whether another compliant (e.g., UPI compliant) endpoint is on the link. The agent may continue to switch between the transmitter detect and L1b states until an expected transmitter signal is received to identify the presence of a transmitter of a remote agent, causing the agent to exit the transmitter detect state, as described above (e.g., to a polling state).

Polling state: receiver adapts, initializes drift buffer and locks on bits/bytes (e.g. identifies symbol boundaries). Lanes may be deskewed. A remote agent may cause an exit to a next state (e.g. a Link Width State) in response to an acknowledge message. Polling can additionally include a training sequence lock by locking to an EOS and a training sequence header. Lane to lane skew at remote transmitter may be capped at a first length for top speed and a second length for slow speed. Deskew may be performed in a slow mode as well as an operational mode. Receiver may have a specific maximum to deskew lane-to-lane skew, such as 8, 16, or 32 intervals of skew. Receiver actions may include latency fixing. Receiver actions, in one embodiment, can be completed on successful deskew of a valid lane map. A successful handshake can be achieved, in one example, when a number of consecutive training sequence headers are received with acknowledgements and a number of training sequences with an acknowledge are transmitted after the receiver has completed its actions.

Link width state: agent communicates with the final lane map to remote transmitter. Receiver receives the information and decodes. Receiver may record a configured lane map in a structure after checkpoint of a previous lane map value in a second structure. Receiver may also respond with an acknowledge (“ACK”). May initiate an in-band reset. As one example, first state to initiate in-band reset. In one embodiment, exit to a next state, such as flit configuration state, is performed in response to the ACK. Further, prior to entering low power state, a reset signal may also be generated if the frequency of a wake detect signal occurrence drops below a specified value (e.g. 1 every number of unit intervals (UIs), such as 4K UI). Receiver may hold current and previous lane maps. Transmitter may use different groups of lanes based on training sequences having different values. Lane map may not modify some status registers in some embodiments.

Flitlock configuration state: entered by a transmitter but the state is considered exited (i.e. secondary timeout moot) when both transmitter and receiver have exited to a blocking link state or other link state. Transmitter exit to a link state, in one embodiment, includes start of a data sequence (SDS) and training sequence (TS) boundary after receiving a planetary alignment signal. Here, receiver exit may be based on receiving an SDS from a remote transmitter. This state may be a bridge from agent to link state. Receiver identifies SDS. Receiver may exit to blocking link state (BLS) (or a control window) if SDS received after a descrambler is initialized. If a timeout occurs, exit may be to reset state. Transmitter drives lanes with a configuration signal. Transmitter exit may be to reset, BLS, or other states based on conditions or timeouts.

Compliance state: entered from the Transmitter calibrate state. One device (acting as master) can send a compliance pattern to another device (slave) and the slave can loop back the pattern after re-timing it to its local clock. Can be used to characterize operation of the analog front end on some subset of lanes when loopback is not functional. Compliance state may be utilized for jitter or noise investigation, debug, exploring a link, etc. The Compliance state can drive a supersequence with a transmitter from the master. Receiver looks for a wake on a monitor lane, debounces the wake, drops bad lanes, adapts, and bit locks, etc. The slave transmitter can drive the compliance pattern until its receiver actions are complete. Then loopback is re-timed and non-deskewed. Slave receiver does similar monitor and debounce, etc. actions. Exit may be to a reset state, such as a timed reset, or to a loopback pattern state to start the test, among other examples.

Agent Loopback Marker State: Loopback marker is an agent state but unlike other agent states master and slave actions and exits may be different. Loopback slave may undo any polarity inversion and/or lane reversal but may not descramble or rescramble looped back bits. Acknowledgment exchange may not apply to slave since it is looping back. Since slave may deskew before looping back on symbol boundary, master may not be forced to re-bytelock or re-deskew but the master may re-lock training sequence to avoid locking to some alias. Means to do this may include re-seeding of LFSR, comparing TS and/or EIEOS or some combination of these. The end of the SDS marks the end of loopback setup and the start of pattern generation, checking and counting.

Agent Loopback Pattern State (or Block Link state): In this state, instead of control patterns, a master transmitter can send a test pattern (such as an Interconnect Built-In Self-Test (IBIST) pattern) and its receiver can check for errors in received pattern. For transmitter adaptation both agents can be masters. For a predetermined period, the transmitter can sends a pattern and a remote receiver can compare this pattern and determine a figure of merit or metric for the received pattern which is recorded in a storage element, such as a register. The comparison method and metric may be design dependent (e.g., BER with jitter injection). At the end of the period, both agents can exit to Reset for the backchannel to examine the metric and set up the next iteration of transmitter adaptation.

Transmitting Link State: a link state. Flits are sent to a remote agent. May be entered from a blocking link state and return to a blocking link state on an event, such as a timeout. Transmitter transmits flits. Receiver receives flits. May also exit to a low power link state. In some implementations, transmitting link state (TLS) can be referred to as the L0 state.

Blocking Link State: a link state. Transmitter and receiver are operating in a unified manner. May be a timed state during which the link layer flits are held off while the Physical layer information is communicated to the remote agent. May exit to a low power link state (or other link state based on the design). A blocking link state (BLS), in one embodiment, periodically occurs. The period is referred to as a BLS interval and may be timed, as well as may differ between slow speed and operational speed. Note that the link layer may be periodically blocked from sending flits so that a Physical layer control sequence of a length may be sent, such as during a transmitting link state or a partial width transmitting link state. In some implementations, blocking link state (BLS) can be referred to as a L0 control, or L0c, state.

Partial Width Transmitting Link State: Link state. May save power by entering a partial width state where one or more available lanes of a link are made idle during the partial width transmitting link state. In one embodiment asymmetric partial width refers to each direction of a two direction link having different widths, which may be supported in some designs. Note that speeds may not be altered but width may be. Therefore, flits are potentially sent at different widths. May be similar to a transmitting link state logically; yet, since there is a smaller width, it may take longer to transmit flits. May exit to other link states, such as a low power link state based on certain received and sent messages or an exit of the partial width transmitting link state or a link blocking state based on other events. In one embodiment, a transmitter port may turn idle lanes off in a staggered manner to provide better signal integrity (i.e. noise mitigation) as shown in the timing diagram. Here, non-retry-able flits, such as Null flits, may be utilized during periods where the link width is changing. A corresponding receiver may drop these null flits and turn idle lanes off in a staggered manner, as well as record the current and previous lane maps in one or more structures. Note status and associated status register may remain unaltered. In some implementations, partial width transmitting link state can be referred to as a partial L0, or L0p, state.

Exit Partial Width Transmitting Link State: exit the partial width state. May or may not use a blocking link state in some implementations. The transmitter initiates exit, in one embodiment, by sending partial width exit patterns on the idle lanes to train and deskew them. As one example, an exit pattern start with EIEOS, which is detected and debounced to signal that the lane is ready to start the entry to a full transmitting link state, and may end with SDS or Fast Training Sequence (FTS) on idle lanes. Any failure during the exit sequence (receiver actions, such as deskew not completed prior to timeout) stops flit transfers to the link layer and asserts a reset, which is handled by resetting the link on the next blocking link state occurrence. The SDS may also initialize the scrambler/descrambler on the lanes to appropriate values.

Low Power Link State: is a lower power state. In one embodiment, it is lower power than the partial width link state, since signaling in this embodiment is stopped on all lanes and in both directions. Transmitters may use a blocking link state for requesting a low power link state. Here, receiver may decode the request and respond with an ACK or a NAK; otherwise reset may be triggered. In some implementations, low power link state can be referred to as a L1 state.

In some implementations of UPI, supersequences can be defined, each supersequence corresponding to a respective state or entry/exit to/from the respective state. A supersequence can include a repeating sequence of data sets and symbols. The sequences can repeat, in some instances, until completion of a state or state transition, or communication of a corresponding event, among other examples. In some instances, the repeating sequence of a supersequence can repeat according to a defined frequency, such as a defined number of unit intervals (UIs). A unit interval (UI) can correspond to the interval of time for transmitting a single bit on a lane of a link or system. In some implementations, the repeating sequence can begin with an electrically ordered set (EOS). Accordingly, an instance of the EOS can be expected to repeat in accordance with the predefined frequency. Such ordered sets can be implemented as defined 16 Byte codes that may be represented in hexadecimal format, among other examples. In one example, the EOS of a supersequence can be an EIEOS. An EIEOS can resemble a low frequency clock signal. In one implementation, an EIEOS may be implemented in one of two modes. In a first mode, a traditional EIEOS pattern may be utilized, such as represented in FIG. 8A. For instance, a traditional EIEOS pattern may be repeating sequence of FF00 hexadecimal symbols. A second mode may provide for an EIEOS pattern that is adapted to higher speeds. In one example, the EIEOS pattern in a second mode may be implemented as a repeating sequence of FFFF0000 hexadecimal symbols, such as show in FIG. 8B. A predefined set of data can follow the EOS, such as a predefined number of training sequences or other data. Such supersequences can be utilized in state transitions including link state transitions as well as initialization, among other examples.

In some implementations of an interconnect, terminations of a serial data link can be brought on and off, such as when a link is reset or initialized. This approach can introduce complexity and time into the initialization of a link. In some implementations of UPI, terminations of the link can be maintained including during a reset or re-initialization of the link. Further, UPI can permit hot-plugging of devices. When another device is introduced, either through hot-plugging or otherwise, the voltage characteristics of the lane on which the new remote agent is added will change. The local agent can sense these changes (e.g., pulldowns) in the lane voltage to detect the presence of the remote agent and prompt initialization of the link. State machine states and timers can be defined in the state machine to coordinate the detection, configuration, and initialization of a link without terminations.

As an example, a transmitter of a device, during a receiver detect (“RxDetect”) state, can monitor lanes of a link for the presence of a remote receiver termination, which indicates the presence of a remote device on the other end of the link. A remote receiver termination can generate a pull-down voltage on the link. This can serve as a type of handshake, where the receiver termination causes an exit to the next state (e.g., a Transmitter calibration state). If the handshake does not occur within a predefined time, the monitoring device can abort the initialization, causing a transition back to a reset state before re-entering the RxDetect state to attempt again to identify introduction of a remote device on the link (e.g., in connection with a hot plug event or controlled link bring-up initiated by software, among other examples). During RxDetect, receiver terminations (pulldowns) are to be inserted on all good lanes. Any bad lanes may be dropped before exiting the state and transitioning to another where a detect supersequence is communicated between the devices on the link. Further, the signal generated by the receiver termination can be debounced in that the lanes are checked for a sustained assertion of the signal. In one example, debounce can occur for a period corresponding to the predefined time for monitoring the link during the RxDetect state and may be a multiple of the predefined time, among other examples.

In one implementation, UPI can support re-initialization on an in-band reset without changing the termination values through the screening of a lane by the receiving agent for incoming signaling. The signaling can be used to identify good lanes. As an example, the lane can be screened for any one of a set of pre-defined signals that are to be sent by a transmitter device to facilitate discovery and configuration of the link. In one example, a supersequence can be defined corresponding to one or more initialization or re-initialization tasks. The pre-defined sequence can include an EIEOS followed by additional sequence data. In some instances, as each device on either side of a lane becomes active, the devices can begin sending a supersequence corresponding to a particular initialization state, etc. In one embodiment, two types of pin resets can be supported; power-on (or “cold”) reset and warm reset. A reset initiated by software or originating (in the Physical or another layer) on one agent may be communicated in-band to the other agent. However, due to usage of an embedded clock, an in-band reset may be handled by communication to another agent using an ordered set, such as a specific electrical ordered set or EIOS.

The ordered set can be sent during initialization and a PHY control sequence (or “blocking link state”) can be sent after initialization. The blocking link state can block the link layer from sending flits in order to create periodic windows in which physical layer control data may be communicated. As another example, link layer traffic may be blocked to send a few NULL flits which may be discarded at the receiver. In one example, a link layer blocking control sequence (i.e. a blocking link state (BLS) or L0c state) can include a timed state during which the link layer flits are held off while the PHY information is communicated to the remote agent. Here, the transmitter and receiver may start a block control sequence timer. And upon expiration of the timers, the transmitter and receiver can exit the blocking state and may take other actions, such as exit to reset, exit to a different link state (or other state), including states that allow for the sending of flits across the link.

In one embodiment, link training can be provided and include the sending of one or more of scrambled training sequences, ordered sets, and control sequences, such as in connection with a defined supersequence. A training sequence symbol may include one or more of a header, reserved portions, a target latency, a pair number, a physical lane map code reference lanes or a group of lanes, and an initialization state. In one embodiment, the header can be sent with an acknowledgement (ACK) or negative acknowledgment (NAK), among other examples. As an example, training sequences may be sent as part of supersequences and may be scrambled.

In one embodiment, ordered sets and control sequences are not scrambled or staggered and are transmitted identically, simultaneously and completely on all lanes. A valid reception of an ordered set may include checking of at least a portion of the ordered set (or entire ordered set for partial ordered sets). Ordered sets may include an electrically ordered set (EOS), such as an Electrical Idle Ordered Set (EIOS) or an EIEOS. A supersequence may include a start of a data sequence (SDS) or a Fast Training Sequence (FTS). Such sets and control supersequences can be predefined and may have any pattern or hexadecimal representation, as well as any length. For example, ordered sets and supersequences may be a length of 8 bytes, 16, bytes, or 32 bytes, etc. FTS, as an example, can additionally be utilized for fast bit lock during exit of a partial width transmitting link state. Note that the FTS definition may be per lane and may utilize a rotated version of the FTS.

Supersequences, in one embodiment, can include the insertion of an EOS, such as an EIEOS, in a training sequence stream. When signaling starts, lanes, in one implementation, power-on in a staggered manner. This may result, however, in initial supersequences being seen truncated at the receiver on some lanes. Supersequences can be repeated however over short intervals (e.g., approximately one-thousand unit intervals (or ˜1KUI)). The training supersequences may additionally be used for one or more of deskew, configuration and for communicating initialization target, lane map, etc. The EIEOS can be used for one or more of transitioning a lane from inactive to active state, screening for good lanes, identifying symbol and TS boundaries, among other examples.

Turning to FIG. 9, representations of example supersequences are shown. For instance, an exemplary Detect supersequence 905 can be defined. The Detect supersequence 805 can include a repeating sequence of a single EIEOS (or other EOS) followed by a predefined number of instances of a particular training sequence (TS). In one example, the EIEOS can be transmitted, immediately followed by seven repeated instances of TS. When the last of the seven TSes is sent the EIEOS can be sent again followed by seven additional instances of TS, and so on. This sequence can be repeated according to a particular predefined frequency. In the example of FIG. 9, the EIEOS can reappear on the lanes approximately once every one thousand UIs (˜1KUI) followed by the remainder of the Detect supersequence 905. A receiver can monitor lanes for the presence of a repeating Detect supersequence 905 and upon validating the supersequence 905 can conclude that a remote agent is present, has been added (e.g., hot plugged) on the lanes, has awoke, or is reinitializing, etc. The Detect supersequence 905 may be utilized, for instance, in a Transmitter Detect state, in which transmitters of the devices connected on a link are to send the Detect supersequence 805 on all lanes to identify to the remote agent that the transmitter is present.

In another example, another supersequence 910 can be defined to indicate a polling, configuration, or loopback condition or state. As with the example Detect supersequence 905, lanes of a link can be monitored by a receiver for such a Poll/Config/Loop supersequence 910 to identify a polling state, configuration state, or loopback state or condition. In one example, a Poll/Config/Loop supersequence 910 can begin with an EIEOS followed by a predefined number of repeated instances of a TS. For instance, in one example the EIEOS can be followed by thirty-one (31) instances of TS with the EIEOS repeating approximately every four thousand UI (e.g., ˜4KUI), among other examples.

Supersequences, such as Detect supersequence 905 and Poll/Config/Loop supersequence 910, etc., can potentially be sent substantially throughout the initialization or re-initialization of a link. A receiver, upon receiving and detecting a particular supersequence can, in some instances, respond by echoing the same supersequence to the transmitter over the lanes. The receiving and validation of a particular supersequence by transmitter and receiver can serve as a handshake to acknowledge a state or condition communicated through the supersequence. For instance, such a handshake (e.g., utilizing a Detect supersequence 905) can be used to identify reinitialization of a link. In another example, such a handshake can be utilized to indicate the end of an electrical reset or low power state, resulting in corresponding lanes being brought back up, among other examples. The end of the electrical reset can be identified, for instance, from a handshake between transmitter and receiver each transmitting a Detect supersequence 905.

In another example, lanes can be monitored for supersequences and use the supersequences in connection with the screening of lanes for detect, wake, state exits and entries, among other events. The predefined and predictable nature and form of supersequences can be further used to perform such initialization tasks as bit lock, byte lock, debouncing, descrambling, deskewing, adaptation, latency fixing, negotiated delays, and other potential uses. Indeed, lanes can be substantially continuously monitored for such events to quicken the ability of the system to react to and process such conditions. In some cases, supersequences can be sent within control windows (e.g., L0c control windows) to trigger link state transitions, among other examples.

Training sequences (TSes), in some instances, can include a header and various other fields (e.g., payload) that can be used to communicate information in connection with initialization of a link. For instance, in one example, fields for target latency, state, lane pair number, lane mapping, among other fields can be included. In some implementations, portions of a TS can be scrambled, for instance, by a random or pseudo-random binary sequence (PRBS). In one examples, the TS header can be preserved as cleartext while the remainder (or payload) of the TS is scrambled, for instance, by XORing those portions of the TS with a PRBS, among other examples.

In one implementation, a TS can be sixteen (16) bytes in length and the TS header can occupy the first byte (i.e., byte 0) of the TS. The TS payload can be scrambled and occupy the remaining fifteen bytes. In one example implementation, a TS tail or suffix can include the last few bytes of the TS. For instance, in one example, a scrambling synchronization field can occupy at least three bytes of the TS, for instance bytes 6-8 of the TS. The tail bits of the TS (e.g., bytes 9-15), in this particular implementation, can be maintained as reserved bits. Bits in bytes 6-15 can all be set to 0.

In some implementations, UPI can supports use of a TS header can be utilized instead of or in addition to a TS payload for key initialization parameters. In some implementations, TS payload may be used to exchange initialization parameters like ACKs and lane numbers. DC levels for communicating lane polarity may also be used. However, in some implementations, UPI can implement DC-balanced codes in the TS header for key parameters. For instance, in instances where a TS header is unscrambled, available TS header codes can be defined so that the number of “1”s substantially equal the number “0”s appearing in the TS header fields. DC balance can be realized throughout the remainder of the TS (e.g., the TS payload) by scrambling bits of the TS payload by XORing the bits against a random or pseudorandom binary sequence.

In one example implementation, a PRBS sequence can be utilized with at least 23 bits (PRBS23). The PRBS can be generated according to a particular selected polynomial. In one example, the PRBS can be generated by a similar bit size, self-seeded storage element, such as a linear feedback shift register (LFSR). The LFSR can be a 23-bit Fibonacci LFSR capable of generating a PRBS sequence of over 8 Mb in length. The PRBS can repeat following the end of the sequence. In some implementations, the entirety of the PRBS23 sequence can be used in the scrambling of training sequences included in supersequences used, for instance, in initialization of the link in UPI. In some implementations, a respective LFSR can be provided for each lane of a link, with each LFSR receiving a distinct seed to generate PRBS patterns that vary (and in some cases orthogonal) between adjacent lanes.

While the full length of a PRBS sequence can be used, in some implementations, UPI can support allowing the use of varying lengths of the available PRBS sequence (e.g., the use of only a portion of the PRBS23 sequence). In some examples, a controller of a device can specify that only a portion of the full length of a PRBS sequence be utilized. This can be desirable, for instance, in testing applications where repeatability of bit sequences is desired, among potentially other applications. A software-based controller can specifying varying lengths of the PRBS to be applied. For instance, BIOS of a device can specify the PRBS length to be applied on the link. In some implementations, use of the full length of the PRBS sequence can be the default setting, for instance, so as to maximize the benefits of the lengthy PRBS sequence.

Lane traffic in a transmitting link state (TLS) and training sequences can be scrambled with a PRBS of a particular minimum length (e.g., 23 bits). The starting seed applied to a stream can be varied between the lanes to enhance the electrical benefits of the PRBS on the link. In one example implementations, the PRBS can be generated by a 23 bit Fibonacci LFSR implementing a 6-tap generator polynomial, such as, (x²³+x²¹+x¹⁶+x⁸+x⁵+x²+1).

The starting (on scrambler/descrambler initialization) seed values for lane number modulo 8 may be any value, for instance, 8 hexadecimal values where each one is associated with 2 or 3 of the lanes in a link. Use of such seeds can result in rotating (or staggering) of the PRBS between the lanes. The number of LFSRs can be reduced by using the property that even lane PRBS can be derived from an XOR of PRBS of odd lanes. The EIEOS and header of the training sequences may not scrambled. The entry point of a supersequence on each lane can be initiated (e.g., where the transmitter starts driving) at a different point on each lane. This can enable the lanes to be turned on in a staggered manner in order to reduce noise in the power delivery system. Indeed, each lane can have its own instance of an LFSR. The staggering times can vary by the number of lanes being turned on and may be implementation dependent during initialization. These can be specified in the timing diagrams and timer profiles for partial transmitting width state exit. Further, fast training sequences (FTS) (also discussed below) can also be rotated by lane.

In some instances, scrambling can reduce power supply noise at transmitter and provide a richer frequency spectrum at receiver. The scrambler can be initialized by the first EIEOS transmitted. The descrambler can be synchronized to the scrambler, for instance, through self-seeding. For instance, the received 23 bit pattern can be embedded in a field of the TS as a seed. In one example, the 23 bit seed can be identified from the scrambling of the bits of the scrambling synchronization field. The receiver can utilize the seed value to identify the specific location of the PRBS used to scramble the received TS. For instance, a receiver can identify the seed and load the seed into its own LFSR to synchronize to the PRBS used by the transmitter. In some instances, a receiver may read multiple scrambling synchronization field or multiple TSes in a supersequence in order to seed its own LFSR. Upon detecting and synching to the PRBS of the transmitter however, a receiver can descramble the remainder of the TSes as well as all subsequent TS sent in supersequences during initialization of the link, among other examples.

Supersequences can be used to facilitate bit lock and synchronization on a lane. As discussed above, at least a portion of the supersequences can be scrambled. Returning to the discussion of FIG. 9, a Detect supersequence 905 can be used by a receiver to detect, or lock, the bit and byte edges of the received bit stream and identify which bytes are being sent in the supersequence. For instance, the EIEOS and TS header can be left unscrambled to assist the receiver in more quickly locking to the supersequence. Additionally, the supersequence can be defined to allow the EIEOS (and beginning of the supersequence) to repeat at a relatively short frequency (e.g., to more quickly allow the receiver another chance to detect the EIEOS in the event that the first EIEOS was not accurately detected). For instance, in one example, a supersequence can be defined to repeat every 1KUI or shorter. Such supersequences can further allow more randomized transitions during initialization, as well as simplifying TS lock, latency fixing, and other actions.

Additionally, leaving the EIEOS and TS header unscrambled can allow byte lock to occur and permit the receiver to be able to identify the location of subsequent bytes and symbols (including scrambled TS symbols). For instance, the edge of the unscrambled TS header can be identified and thereby also the start of scrambling synchronization field. Upon detecting the PRBS seed in the scrambling synchronization field, the receiver will know the following PRBS pattern values and will also be able to predict the values of subsequent scrambling synchronization field values. Accordingly, the receiver, upon locking to the PRBS can further utilize the scrambling synchronization field values to facilitate other configuration tasks such as adaptation, deskew, and other tasks.

On multi-lane links, symbols can be sent simultaneously on all lanes by a transmitter, however, link-to-link skew can manifest with some symbols not arriving at the receiver at the same time. Sources of skew can include, for instance, chip differential drivers and receivers, printed wiring board impedance variations, lane wire length mismatches, among other examples. In one embodiment, UPI provides advanced logic to deskew lanes. As an example, the TS boundary after TS lock can be used to deskew the lanes. For instance, TS lock can be used to detect skew (e.g., that a TS is arriving on one lane later than another TS on another one of the link's lanes). An EIEOS can also be used to detect skew. In addition, using the predictability of a synched PRBS pattern, some implementations of UPI may deskew by comparing lane PRBS patterns in the LFSR during specific points in the payload.

In the case of adaptation, electrical characteristics of a lane can be adjusted between a transmitter and receiver based, for instance, on sample data transmitted between the transmitter and receiver. For instance, receiver adaptation can include the transmitter sending a data pattern to the receiver with logic at the receiver adjusting electrical characteristics at the receiver to adapt the lane for the link. Transmitter adaptation can involve the transmitter sending sample data to the receiver and the receiver sending feedback to the transmitter that can be used by the transmitter to make adjustments at the transmitter to adapt the lane. The receiver can continue to send feedback to the transmitter based on the adjustments made at the transmitter.

In one example, adaptation sample data can be embodied through scrambled TS data. As one example, a fixed UI pattern may be utilized to scramble with a bypass to an adaptation state. But by scrambling TS with PRBS23, receiver adaptation may be performed without the bypass. In addition, offset and other errors may be reduced during clock recovery and sampling. The randomness provided through a long PRBS sequence (e.g., PRBS23) can prove an effective sample stream for adaptation. Further, in some implementations, a lane can be set to operate in slow mode to assist the logic in analyzing and adapting to sample data received on the lane. Upon approving the characteristics of the lane through adaptation, the adapted characteristics can be set and applied to the initialization of the link.

Once the link has been successfully calibrated and configured, initialization can end and the link can transition to the transmitting link state (TLS) in which flits begin to be transmitted. In some implementations of UPI, transitions to TLS can be based on planetary alignment on the system. For instance, a planetary alignment signal can indicate an opportunity to transition to TLS. Rather than transitioning at an edge of a supersequence, EIEOS, or TLS, some implementations of UPI can utilize a start of data sequence (SDS) symbol sent in accordance with the planetary alignment to end initialization and transition to TLS. In one example, an SDS can be sent anywhere in an initialization bit stream. Accordingly, a receiver can continuously scan received bits for the SDS to hasten ending of the initialization in accordance with a planetary alignment.

In some examples, agents and devices may be provided to support enhanced features of UPI. For instance, a UPI link may be configured to support enhanced transmission speeds. In such instances (as well as traditional UPI speeds), an enhanced mode may be provided in which a lower frequency EIEOS patterns is utilized, such as shown and described in connection with FIG. 8B. A lower frequency EIEOS pattern (embodied as a repeating FFFF0000 signal) may assist agents in more efficiently processing synchronization and wake patterns and supersequences that include or rely upon one or more embedded EIEOSes. An enhanced mode may additionally provide for larger link widths, such that n lanes (e.g., where n>30) may be supported. In both the case of systems supporting the enhanced lower frequency EIEOS and increased link widths, logic may be provided (e.g., in a corresponding agent, device, or controller) such that the device is backward compatible with and also supports traditional or initial UPI configurations. For instance, a register may be provided through which settings of a particular device may be set to indicate whether the device is to utilize a low frequency EIEOS pattern (e.g., 0000FFFF) or a traditional EIEOS pattern (e.g., 00FF) in communications on the link. The same or another register may indicate whether the device supports links with enhanced link widths (e.g., 24+ lane links) or traditional UPI link widths (e.g., 20 lane links). To provide for backward compatibility between links with added lanes and those with a traditional number of lanes, hardware of the device may provide for backward compatible, for instance, by dictating that added lanes be connected in the center of the port (i.e., rather than by providing added lanes at either one of the ends of the port).

Additional enhancements may be provided in some implementations. In one example, to accommodate repeater devices (which may not natively support mirroring of pulldown voltages from one device connected through the repeater to the other (and vice versa)), the link training status state machine (LTSSM) of the interconnect (as managed at agent by respective state machine logic) may be augmented to support an additional low power state, such as a beacon (or L1b) low power state. This may ensure that endpoint devices are discovered during the transmitter detect state, by orchestrating retries of the transmitter detect state, broken by intermittent transitions to the L1b low power state (e.g., to preserve power while waiting for the arrival of another device (e.g., through hot-plugging or due to delays on the remote device) on a link that includes a repeater device. As an another example, link adaptation may be enhanced by providing for stepwise serial adaptation of both sides of a link (e.g., with a first adaptation stage involving one device as master and a subsequent second adaptation stage involving the other device as master), among other example modifications and enhancements.

As noted above, a device may be provided which is able to alternatively support two different link widths. In one example, a first mode may provide for links with 24 lanes, while a second alternate model provides for links with 20 lanes. Such a change may also affect the manner in which various interconnect features are provided. For instance, as shown in FIGS. 10A-10B, a traditional 20 lane UPI implementation may involve interleaving or “swizzling” bits across multiple nibbles. For instance, FIG. 10A illustrates a representation of transmission of consecutive flits overlapped on a number of lanes in a traditional 20-lane configuration (or operation mode). For instance, FIG. 10A shows a representation of five overlapping 192-bit flits sent over a 20 lane link (the lanes represented by columns 0-19). Each cell of FIG. 10A represents a respective “nibble” or grouping of four bits (e.g., bits 4 n+3:4 n) included in a flit sent over a 4UI span. For instance, a 192 bit flit can be divided into 48 four-bit nibbles. In one example, nibble 0 includes bits 0-3, nibble 1 includes bits 4-7, etc. The bits in the nibbles can be sent so as to overlap, or be interleaved (e.g., “swizzled”), such that higher-priority fields of the flit are presented earlier, error detection properties (e.g., CRC) are retained, among other considerations. Indeed, a swizzling scheme can also provide that some nibbles (and their respective bits) are sent out of order. In some implementations, a swizzling scheme can be dependent on the architecture of the link layer and format of the flit used in the link layer.

The bits (or nibbles) of a flit with a length that is not a multiple of the active lanes can be swizzled, such as according to the example of FIG. 10A. For instance, during the first 4UI, nibbles 1, 3, 5, 7, 9, 12, 14, 17, 19, 22, 24, 27, 29, 32, 34, 37, 39, 42, 44 and 47 can be sent. Nibbles 0, 2, 4, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 33, 36, 38, 41, 43, and 46 can be sent during the next 4UI. In UIs 8-11, only eight nibbles remain of the first flit. These final nibbles (i.e., 10, 15, 20, 25, 30, 40, 45) of the first flit can be sent concurrently with the first nibbles (i.e., nibbles 2, 4, 7, 9, 12, 16, 20, 25, 30, 35, 40, 45) of the second flit, such that the first and second flits overlap or are swizzled. Using such a technique, in the present example, five complete flits can be sent in 48UI, with each flit sent over a fractional 9.6 UI period.

In some instances, swizzling can result in periodic “clean” flit boundaries. For instance, in the traditional example of FIG. 10A, the starting 5-flit boundary (the top line of the first flit) may also be referred to as a clean flit boundary since all lanes are transmitting starting nibble from same flit. Agent link layer logic can be configured to identify swizzling of lanes and can reconstruct the flit from the swizzled bits. Additionally, physical layer logic can include functionality for identifying when and how to swizzle a stream of flit data based on the number of lanes being used at the moment. Turning to the example of FIG. 10B, the transmission of three flits over an enhanced 24 lane link is illustrated, borrowing from the conventions used in FIG. 10A. Specifically, each cell of FIG. 10B may represent a respective nibble included in a flit sent over a 4UI span (with the same 192 bit flit divided into 48 four-bit nibbles, as shown again in FIG. 10B. Utilizing the 24 lane link, the logic utilized to implement and decode the swizzling of bits across multiple flits (as in the traditional UPI implementation) may be disabled or set aside, as flits sent over an example 24 lane link are sent with clean flit boundaries, as shown in FIG. 10B. In a device supporting backward compatibility (to function in either the traditional or enhanced UPI mode of operation), logic utilized for swizzling may be preserved.

UPI may provide for 16-bit cyclic redundancy check (CRC) fields to be included in the flits sent over lanes (e.g., 24 or 20) of a link and populated with 16-bit CRC codes generated according to a particular CRC polynomial. For instance, the CRC polynomial may be selected such that a CRC syndrome generated from the CRC can be used to identify specific bit errors, which can then be mapped to specific lanes of a link. In one example, syndrome properties of a 0x1f053 16-bit polynomial calculation can be used to identify bad lanes. Such a CRC polynomial can possess capabilities that allow all 1, 2, 3 bit errors and almost all 4 bit errors in an example flit to be identified. A receiving agent may calculate the syndrome from the CRC code and determine the specific bits of the flit affected by any bit error(s) communicated through the CRC code (e.g., by consulting a mapping of possible syndrome values to bit numbers (or even consecutive bit numbers for 2 bit errors, etc.). By identifying the specific bits within a flit that had errors (based on the syndrome), the specific lanes may be identified on which that bit was sent. Bit errors that occur on a recurring basis on a single lane (or lanes) may cause remedial action to be initiated to correct the lane error. Mapping bit errors to lanes may be based on which UPI mode is enabled for a particular link. For instance, when a 24-lane link mode is enabled, a mapping of bit numbers to lanes (such as shown in Table 1 below) may be consulted that is specific to the 24-lane link mode. A different corresponding mapping may be provided for other link width modes (e.g., a 20-lane link), among other examples.

TABLE 1 Bit Error Mapping for Flits sent on 24-Lane Links Lane Number Lane Number MSb LSb (w/o reversal) (w/ reversal) 191 184 23 0 183 176 22 1 175 168 21 2 167 160 20 3 159 152 19 4 151 144 18 5 143 136 17 6 135 128 16 7 127 120 15 8 119 112 14 9 111 104 13 10 103 96 12 11 95 88 11 12 87 80 10 13 79 72 9 14 71 64 8 15 63 56 7 16 55 48 6 17 47 40 5 18 39 32 4 19 31 24 3 20 23 16 2 21 15 8 1 22 7 0 0 23

Enhanced implementations may alternatively support increased link widths of n nominal lanes. Training sequences may be defined to indicate lane numbers for any link width configuration (e.g., to number lanes from 0 to n−1). While increased link widths may be supported while supporting backward capability to smaller, traditional link widths (e.g., 20 lane links), care is to be taken, as some signals defined within UPI may be lane specific. As lane reversal may be supported, failure to appropriately map certain UPI signals to their appropriate lanes may cause errors and/or performance degradation. For instance, PRBS patterns may be sent on a per-lane basis, with each LFSR seeded with a lane-specific seed to generate coordinating PRBS patterns on neighboring lanes of the link. As another example, compliance patterns (which may likewise be based on PRBS patterns) may be lane specific. FTS signals may also be lane dependent, among other examples. While additional multiplexer (“Mux”) hardware may be theoretically provided to manage consistent lane numbering in both 20-lane and 24-lane modes, where lane reversal is possible, in some implementations, common Mux hardware may be utilized to support varying numbers of lanes in various alternative operating modes. Such Mux hardware can be further provided to minimize the complexity of circuitry and connections to the Mux hardware as well as latency introduced by higher input multiplexers.

In one example, illustrated in FIGS. 11A-11B, a backward compatible multiplexer may be implemented by an array of two input multiplexer components. The multiplexer may facilitate lane reversal, such that when a reversal signal is provided to the multiplexer (e.g., to each multiplexer component in the array), it causes each multiplexer to select the lane corresponding to the lane reversal. As an example, the multiplexer shown in the example of FIG. 11A demonstrates a multiplexer capable of supporting link widths up to 24 lanes (e.g., numbered 0-23). For a 24 lane link, a first input of each of the multiplexer components may be provided with a lane according to a normal (non-reversed) lane configuration. For instance, in an array or sequence of multiplexer components (MUX), a first MUX A (e.g., 1105) may take lane 0 as one of its inputs, a second MUX B (e.g., 1110) may take lane 1 as one of its inputs, and so on until a final MUX X (e.g., 1115) in the sequence, which may take the last lane (lane 23) in the link. To facilitate lane reversal, the other input of each MUX may be provided with lane inputs according to a reversed lane order. For instance, MUX A 1105 may take lane 23 as the second of its two inputs, MUX B 1110 may take lane 22 as the second of its two inputs, and so on until the last MUX X 1115 takes the first lane, lane 0, at the second of its two inputs. As a result, when reversal is activated, each of MUXes may cause data on the second of its inputs to be output onto a corresponding lane.

As noted above, the multiplexer array 1100 shown in the example of FIG. 11A-11B may facilitate lane reversal and backward compatible between two different link widths (e.g., 24 and 20 lane links). This may be facilitated by defining that the individual MUXes be assigned to lanes in an outside-in manner, such that lanes are “added” to the center (i.e., rather than at the edge. To illustrate, FIG. 11B shows use of the same multiplexer infrastructure utilized for facilitating lane reversal in a 24-lane configuration for lane reversal in a 20-lane configuration. For a 20-lane implementation, only 20 of the MUX components may be utilized. However, rather than disabling or omitting MUX components at the end of the array (e.g., the four MUX components A-D or U-X (e.g., which would necessitate the use of 3-input MUXes)), the MUX components (and corresponding ports) at the center (e.g., MUXes K-N) may be disabled for the reduced lane configuration. Similarly, should smaller link widths be provided for, the same MUX architecture may be reused, with surplus MUX components being disabled outwardly from the center of the port. As an example, in an 8-lane configuration, the MUX architecture of the example of FIG. 11A may again be reused, but with 8 of the MUXes (e.g., A-D and U-X) utilized and the remaining MUXes (e.g., E-T) disabled, among other examples. In this manner, a MUX architecture may be provided that is topology-based (e.g., rather than tied to a particular link width).

In one example, an example EIEOS can emulate a low frequency clock signal, such as either a repeating FF00 or FFFF0000 signal. EIEOSes may be utilized in a variety of contexts. For instance, EIEOSes may be utilized within a variety of supersequences for use in training of links in an interconnect (such as discussed herein). EIEOSes may be additionally used in various link training tasks, such as latency fixing and lane debouncing. In the case of debouncing, transients can be introduced on lanes as a result of a variety of conditions. For instance, the addition or powering-on of a device can introduce transients onto the lane. Additionally, voltage irregularities can be presented on a lane because of poor lane quality or electrical failure. In some cases “bouncing” on a lane can produce false positives, such as a false EIEOS. However, in some implementations, while supersequences can begin with an EIEOS, defined supersequences can further include additional sequences of data as well as a defined frequency at which the EIEOS will be repeated. As a result, even where a false EIEOS appears on a lane, a logic analyzer at the receiver can determine that the EIEOS is a false positive by validating data that succeeds the false EIEOS. For instance, if expected TS or other data does not follow the EIEOS or the EIEOS does not repeat within a particular one of the predefined frequencies of one of the predefined supersequences, the receiver logic analyzer can fail validation of the received EIEOS. As bouncing can occur at start up as a device is added to a line, false negatives can also result. For instance, upon being added to a set of lanes, a device can begin sending a Detect supersequence 905 to alert the other side of the link of its presence and begin initialization of the link. However, transients introduced on the lanes may corrupt the initial EIEOS, TS instances, and other data of the supersequence. However, a logic analyzer on the receiving device can continue to monitor the lanes and identify the next EIEOS sent by the new device in the repeating Detect supersequence 905, among other examples.

In one example, a transmitting device can attempt to enter a particular state. For instance, the transmitting device can attempt to activate the link and enter an initialization state. In another example, the transmitting device can attempt to exit a low power state, such as an L1 state, among other examples. In some instances of an L1 state, the L1 state can serve as a power savings, idle, or standby state. Indeed, in some examples, main power supplies may remain active in the L1 state. In exiting an L1 state, a first device can send a supersequence associated with transitioning from the L1 state to a particular other state, such as an L0 transmitting link state (TLS). The supersequence, as in other examples, can be a repeating sequence of an EOS (e.g., traditional or low frequency EIEOS) followed by a predetermined number of TSes such that the EOS is repeated at a particular predefined frequency. In one example, a Detect supersequence can be used to exit the L1 or other low power state. A receiving device can receive and validate the data, identifying the supersequence, and the receiving device can complete the handshake with the transmitting device by sending the supersequence back to the transmitting device.

With both the transmitting and receiving devices receiving the same supersequence, each device can further perform additional initialization tasks utilizing the supersequences. For instance, each device can perform debouncing, bit lock, byte lock, descrambling, and deskewing utilizing the supersequences. Additional initialization information can be communicated through the headers and payloads of the TSes included in the supersequences. When the link is initialized, a start data send (SDS) sequence can be sent, in some cases, interrupting the supersequence (e.g., sent in the middle of a TS or EIEOS) and the respective devices on either side of the link can prepare for the synchronized entry into TLS. In TLS, or an “L0” state, supersequences can be ended and flits can be transmitted utilizing the Link layer of the protocol stack.

While in TLS, the Physical layer may still be provided limited opportunities to perform control tasks. For instance, bit errors and other errors may be identified on one or more lanes during an L0 state. In one implementation, a control state L0c can be provided. The L0c state can be provided as a periodic window within the TLS to allow Physical layer control messages to be sent between streams of flits sent through the Link layer. For instance, an L0 state can be subdivided into L0c intervals. Each L0c interval can begin with a L0c state or window in which Physical layer control codes and other data can be sent. The remainder of the L0c interval can be dedicated to the sending of flits. The length of the L0c interval and L0c state in each interval can be programmatically defined, for instance by BIOS of one or more devices or another software-based controller, among other examples. The L0c state can be exponentially shorter than the remainder of an L0c interval. For instance, in one example, the L0c can be 8UI while the remainder of the L0c interval is on the order of 4KUI, among other examples. This can allow windows in which relatively short, predefined messages can be sent without substantially disrupting or wasting link data bandwidth.

L0c state message can communicate a variety of conditions at the Physical layer level. In one example, one device can initiate a reset of the link or a lane, for instance, based on bit errors or other errors in excess of a particular threshold amount. Such errors can also be communicated in L0c windows (such as preceding L0c windows). The L0c state can also be leveraged to realize other in-band signaling, such as signaling for use in aiding or triggering transitions between other link states. In one example, L0c messages can be utilized to transition a link from an active L0 state to a standby or low power state, such as an L1 state. For instance, a particular L0c state can be used to communicate a L1 entry request, a reset request, or other request. The request can involve the sending of a corresponding supersequence defined to indicate an entry or exit from a link state, among other examples.

In addition (or as an alternate) to handshaking using L0c codes, supersequences, such as Detect supersequence, can be sent in connection with resetting and re-initializing the link. Further handshaking can occur between the devices as the supersequences sent by a first device and echoed by the second, receiving device. Supersequences can be used, as described above, to assist in the reinitialization of the link including debouncing, bit lock, byte lock, descrambling, and deskewing the lanes of the link. Further, the devices can utilize the timer (e.g., embodying the L0c interval) to synchronize entry of the devices and the link into the requested state, among other examples.

In one embodiment, a platform can include a clock that serves as the reference clock for devices in the system. The clock can be embedded in the data so there are no separate clock lanes. The clock signal can be extracted from received data. Further, the flits sent over the lanes can be scrambled to facilitate clock recovery. The receiver clock recovery unit, as one example, can deliver sampling clocks to a receiver (i.e. the receiver recovers clock from the data and uses it to sample the incoming data). Receivers in some implementations continuously adapt to an incoming bit stream. By embedding the clock, pinout can be potentially reduced. However, embedding the clock in the in-band data can alter the manner in which in-band reset is approached. In one embodiment, a blocking link state (BLS) can be utilized after initialization. Also, electrical ordered set supersequences may be utilized during initialization to facilitate the reset (e.g., as described above), among other considerations. The embedded clock can be common between the devices on a link and the common operational clock can be set during calibration and configuration of the link.

As noted above, adaptation of lanes on a link may be supported in UPI. The Physical layer can support both receiver adaptation and transmitter, or sender, adaptation. For instance, as illustrated in the simplified block diagram 1200 a-b of FIGS. 12A-12B, in receiver adaptation, the transmitter (e.g., of device 1205) on a lane can send sample data to the receiver (e.g., of device 1210) which the receiver logic can process to identify shortcomings in the electrical characteristics of the lane and quality of the signal. The receiver can then make adjustments to the calibration of the lane to optimize the lane based on the analysis of the received sample data. In the case of transmitter adaptation, the receiver (of device 1210) can again receive sample data and develop metrics describing the quality of the lane but in this case communicate the metrics to the transmitter (e.g., using a backchannel, such as via a software manager (e.g., 1215), a sideband channel, or other mechanism) to allow the transmitter (of device 1205) to make adjustments to the lane based on the feedback.

FIG. 12A illustrates an example adaptation process where a first one of the devices (e.g., 1205) acts as the loopback master, while FIG. 12B illustrate a counterpart example where the second of the devices (e.g., 1210) acts as loopback master. In some implementations, receiver adaptation can be initiated at the start of the Polling state using the Polling supersequence sent from the remote transmitter. Similarly, transmitter adaptation can be done by repeating the following for each transmitter parameters. In some implementations, both agents (of devices 1205 and 1210) can enter Loopback Pattern state as masters and transmit the specified pattern. In such an example, adaptation of the link may be performed concurrently for both directions of the link (effectively performing the procedures illustrated in FIGS. 12A and 12B in parallel). In such examples, both receivers can measure the metric (e.g. BER) for that particular transmitter setting at a remote agent. Both agents can go to Loopback Marker state and then Reset and use backchannels (slow mode or sideband) to exchange metrics. Based on these metrics, the next transmitter setting can be identified. Eventually the optimal transmitter setting can be identified and saved for subsequent use (e.g., during the active link state). This process, in some implementations, may be performed concurrently at each device 1205, 1210, with each device being both master and slave in the respective adaptations of the link.

In an alternate implementation, adaptation of a link may be completed in two stages, a first stage for adaptation of the link in a first direction, and a second stage for adaptation of the link in the other second direction. In such an implementation, the procedures represented by the illustrations in FIGS. 12A-12B may be carried out sequentially with adaptation of the link in the direction from device 1205 to device 1210 being carried out first (with device 1205 as master as in the example of FIG. 12A). When this direction of the link has been successfully adapted, the roles of the device's agents may be reversed in a second stage, with device 1210 serving as the master (and device 1205 as the slave, as in FIG. 12B) and adaptation being performed for the link in the direction from device 1210 to device 1205.

In either alternative implementation of adaptation of a UPI link, a transmitter of an agent can transmit to a remote receiver a random, or pseudo random pattern. In some instances, scrambled supersequences can be used as the pattern. Logic at the receiver can determine characteristics of one or more lanes of the link and generate metric data describing such characteristics. In the case of receiver adaptation, the receiver can attempt to determine optimal configurations for a lane based on the metrics and apply these configurations at the receiver. In the case of transmitter adaptation, the receiver can communicate metrics to the transmitter for use by the transmitter agent to configure and adapt the lane based on the metric. In either instance, in some implementations, hardware or software can be utilized to assess different transmitter settings in algorithmic order to determine the optimal settings. For instance, metrics may be communicated to a software manager (e.g., 1215), which may be used to determine a figure of merit describing aspects of the transmitter and/or receiver settings (e.g., implemented to identify a statistically weighted function of eye height, eye width and multiple other receiver values (e.g., attenuator, clock data recovery (CDR), continuous time offset cancellation (CTOC), decision feedback equalizer (DFE), reference voltage (vref), boost, etc.). Software may then apply one or more optimization or setting adjustment algorithms to determine the next transmitter setting to be tried and may repeat the loopback adaptation process until a best setting of the transmitter is determined. When this process is completed for both transmitters on the link, the adaptation of the link may be considered complete.

Receiver adaptation can be initiated at the start of the Polling state using the Polling supersequence sent from the remote transmitter. Similarly, transmitter adaptation can be done by repeating the following for each transmitter parameters. Both agents can enter Loopback Pattern state as masters and transmit specified pattern. Further, both receivers can measure the metric (e.g. BER) for that particular transmitter setting at a remote agent. Both agents can go to Loopback Marker state and then Reset and use backchannels (slow mode or sideband) to exchange metrics. Based on these metrics, the next transmitter setting can be identified. Eventually the optimal transmitter setting can be identified and saved for subsequent use.

Some systems and devices utilizing UPI can be deterministic such that their transactions and interactions with other systems, including communications over an UPI link, are synchronized with particular events on the system or device. Such synchronization can take place according to a planetary alignment point or signal corresponding to the deterministic events. For instance, a planetary alignment signal can be used to synchronize state transitions, including entry into a link transmitting state, with other events on the device. In some instances, sync counters can be employed to maintain alignment with a planetary alignment of a device. For instance, each agent can include a local sync counter which is initialized by a planetary aligned signal (i.e., common and simultaneous (except for fixed skew) to all agents/layers which are in sync). This sync counter can count alignment points correctly even in powered down or low-power states (e.g., L1 state) and can be used to time the initialization process (after reset or L1 exit), including the boundaries (i.e., beginning or end) of an EIEOS (or other EOS) included in a supersequence utilized during initialization. Such supersequences can be fixed in size and greater than max possible latency on a link. EIEOS-TS boundaries in a supersequence can thus be used as a proxy for a remote sync counter value.

Further, UPI can support master-slave models where a deterministic master device or system can drive timing of interaction with another device according to its own planetary alignment moments. Further, in some examples, master-master determinism can be supported. Master-master or master slave determinism can ensures that two or more link-pairs can be in lock-step at the Link layer and above. In master-master determinism, each direction's exit from initialization can be controlled by respective transmitter. In the case of master-slave determinism, a master agent can controls the determinism of the link pair (i.e., in both directions) by making a slave transmitter initialization exit wait for its receiver to exit initialization, for instance, among other potential examples and implementations.

In some implementations, a synchronization (or “sync”) counter can be utilized in connection with maintaining determinism within an UPI environment. For instance, a sync counter may be implemented to count a defined amount, such as 256 or 512 UI. This sync counter may be reset by an asynchronous event and may count continuously (with rollover) from then (potentially even during a low power link state). Pin-based resets (e.g., power on reset, warm reset) may be synchronizing events that reset a sync counter, among other example. In one embodiment, these events can occur at two sides with skew less (and, in many cases, much less) than the sync counter value. During initialization, the start of the transmitted exit ordered set (e.g., EIEOS) preceding a training sequence of a training supersequence may be aligned with the reset value of the sync counter (e.g., sync counter rollover). Such sync counters can be maintained at each agent on a link so as to preserve determinism through maintaining constant latency of flit transmissions over a particular link.

Control sequences and codes, among other signals, can be synchronized with a planetary alignment signal. For instance, EIEOS sequences, BLS or L0c windows (and included codes), SDSes, etc. can be configured to be synchronized to a planetary alignment. Further, synchronization counters can be reset according to an external signal, such as a planetary alignment signal from a device so as to itself be synchronized with the planetary alignment, among other examples.

Sync counters of both agents on a link can be synchronized. Resetting, initializing, or re-initialization of a link can include a reset of the sync counters to realign the sync counters with each other and/or an external control signal (e.g., a planetary alignment signal). In some implementations, sync counters may only be reset through an entry into a reset state. In some instances, determinism can be maintained, such as in a return to an L0 state, without a reset of the sync counter. Instead, other signals already tuned to a planetary alignment, or other deterministic event can be used as a proxy for a reset. In some implementations, an EIEOS can be used in a deterministic state entry. In some instances, the boundary of the EIEOS and an initial TS of a supersequence can be used to identify a synchronization moment and synchronize sync counters of one of the agents on a link. The end of an EIEOS can be used, for instance, to avoid the potential of transients corrupting the start boundary of the EIEOS, among other examples.

Latency fixing can also be provided in some implementations of UPI. Latency can include not only the latency introduced by the transmission line used for communication of flits, but also the latency resulting from processing by the agent on the other side the link. Latency of a lane can be determined during initialization of the link. Further, changes in the latency can also be determined. From the determined latency, latency fixing can be initiated to compensate for such changes and return the latency expected for the lane to a constant, expected value. Maintaining consistent latency on a lane can be critical to maintaining determinism in some systems.

Latency can be fixed at a receiver link layer to a programmed value in some implementations using a latency buffer in conjunction with determinism and enabled by starting a detect (e.g., by sending a Detect supersequence) on a sync counter rollover. Accordingly, in one example, a transmitted EIEOS (or other EOS) in Polling and configuration can occur on a sync counter rollover. In other words, the EIEOS can be precisely aligned with the sync counter, such that a synchronized EIEOS (or other EOS) can serve as a proxy, in some instances, for the sync counter value itself, at least in connection with certain latency fixing activities. For instance, a receiver can add enough latency to a received EIEOS so that it meets the dictated target latency at the Physical layer-Link layer interface. As an example, if the target latency is 96 UI and the receiver EIEOS after deskew is at sync count 80 UI, 16 UI of latency can be added. In essence, given the synchronization of an EIEOS, latency of a lane can be determined based on the delay between when the EIEOS was known to be sent (e.g., at a particular sync counter value) and when the EIEOS was received. Further, latency can be fixed utilizing the EIEOS (e.g., by adding latency to the transmission of an EIEOS to maintain a target latency, etc.).

Latency fixing can be used within the context of determinism to permit an external entity (such as an entity providing a planetary alignment signal) to synchronize the physical state of two agents across the link in two directions. Such a feature can be used, for example, in debugging problems in the field and for supporting lock-step behavior. Accordingly, such implementations can include external control of one or more signals that may cause the Physical layer to transition to a transmitting link state (TLS) on two agents. Agents possessing determinism capabilities can exit initialization on a TS boundary, which is also potentially the clean flit boundary when or after the signal is asserted. Master-slave determinism may allow a master to synchronize the Physical layer state of master and slave agents across the link in both directions. If enabled, the slave transmitter exit from initialization can depend on (e.g., follow or be coordinated with) its receiver exit from initialization (in addition to other considerations based on determinism). Agents which have Determinism capability may additionally possess functionality for entering a BLS or L0c window on a clean flit, among other examples.

In some implementations, determinism in UPI can include facilitating the ability of one agent to determine and apply a delay based on a deterministic signal. A master can send an indication of a target latency to a remote agent. The remote agent can determine actual latency on a lane and apply a delay to adjust the latency to meet the target latency (e.g., identified in a TS). Adjusting the delay or latency can assist in facilitating the eventual synchronized entry into a link transmitting state at a planetary alignment point. A delay value can be communicated by a master to a slave, for instance, in a TS payload of a supersequence. The delay can specify a particular number UIs determined for the delay. The slave can delay entry into a state based on the determined delay. Such delays can be used, for instance, to facilitate testing, to stagger L0c intervals on lanes of a link, among other examples.

As noted above, a state exit can be take place according to a planetary alignment point. For instance, an SDS can be sent to interrupt a state supersequence can to drive transition from the state to another state. The sending of the SDS can be timed to coincide with a planetary alignment point and, in some cases, in response to a planetary alignment signal. In other instances, the sending of an SDS can be synchronized with a planetary alignment point based on a sync counter value or other signal synchronized to the planetary alignment. An SDS can be sent at any point in a supersequence, in some cases, interrupting a particular TS or EIEOS, etc. of the supersequence. This can ensure that the state transitions with little delay while retaining alignment with a planetary alignment point, among other examples.

In some implementations, high speed links, such as those supporting and utilizing UPI, can be constrained in length due to the electrical demands on the physical wires implementing the links. Link extending devices, such as repeater, redrivers, and retimers, can be utilized, in some implementations, to effectively “splice” together link sections to form a link with a length in excess of traditional constraints. For instance, electrical driver/receivers in an implementation of an UPI system can be optimized to electrical channels of limited length and bandwidth (e.g. 24″ of FR4 at 10.4 Gbs). This can be more than acceptable for geometrically smaller architectures, but for systems employing larger form factors, such as server racks and other more sizable high speed systems, extension, or repeater, devices, such as retimers or redrivers, may be employed to extend the length of the link.

As signaling frequencies of serial interconnects (e.g., PCIe, USB, UPI, TBT, DP, etc.) increase, the channel lengths that can be driven economically get shorter. At the same time, new platform configurations (e.g., server racks) often need longer channel lengths. Some implementations attempt to address high channel attenuation by utilizing low loss materials for longer channels, however, the use of such materials can become prohibitively expensive. Repeater devices (inclusive of retimers and redrivers) may be utilized as an alternative solution to extend the length of a high-speed link (as in UPI).

FIG. 13 is a simplified block diagram 1300 illustrating an example implementation of link connecting two devices 1305, 1310, where the link is extended using a repeater device 1315. Each device 1305, 1310 send data at its respective transmitter (e.g., Tx A and Tx B) and the data may be received at a receiver (e.g., Rx R₁ and Rx R₂) of the repeater 1315 and then forwarded (on a respective transmitter Tx R₁ and Tx R₂ of the repeater) on to the receiver (e.g., Rx B, Rx A) of the destination device. In some cases, multiple repeater may be inserted in a link to further extend the physical length of the link.

While repeaters (e.g., 1315) may prove useful in extending the physical reach of a link, traditional repeaters may undermine some of the signaling defined within an interconnect protocol, such as UPI. For instance, to support link state transitions and link configuration activities that make use of the detection of a defined receiver pulldown voltage, each device 1305, 1310 can include pulldown detection logic configured to identify voltages on its transmitter (e.g., Tx A and Tx B) corresponding to an expected pulldown voltage from another device (a receiver) present on the link. Such pulldown voltages can serve, for example, as step in a handshake to exit a detect state and make forward progress toward an active link state. For instance, a receiver detect (Rx Detect) state may involve monitoring a transmitter port for a pulldown voltage as evidence that another device is connected on the link and available to receive further signals from the device (e.g., in connection with initialization and training of the link). However, the inclusion of a repeater (e.g., 1315) can interfere and undermine the ability of a pulldown voltage from the other device (e.g., 1310) to be detected by a particular device (e.g., 1305). For instance, while the insertion of the terminations of Device B 1310 will generate a pulldown voltage (e.g., 1325 a) on link segment 1320 b with characteristics that comply with the pulldown voltage expected by Device A 1305 during receiver detect state monitoring, the pulldown voltage 1325 a will ordinarily only be detectable at the transmit side (Tx R₂) of the repeater 1315 and will not be visible at the transmitter (Tx A) of Device A 1305, which is monitoring lane segment 1320 a for a pulldown voltage from Device B 1310. However, Device A 1305, in this example, will detect a pulldown voltage on link segment 1320 a, although the pulldown voltage (e.g., 1325 b) will be from the terminations of the repeater 1315 and not the terminations of Device B 1310. In this case, not only can Device A not detect a pulldown voltage generated by Device B, but Device A will always detect a pulldown voltage (e.g., 1325 b), from the repeater 1315, even if there is no endpoint device on the other end of link (i.e., on the other side of the repeater). The same is true in the other direction, as Device B will only detect the pulldown voltage 1325 d from the repeater 1315 (on link segment 1320 c), with the pulldown voltage of interest (e.g., 1325 c on link segment 1320 d)) from Device A instead being received and blocked by the repeater 1315. Accordingly, a handshake defined within a receiver detect state may be compromised by the presence of a retimer, as shown in the example of FIG. 13.

Returning to the discussion of the state machine illustrated in FIG. 7, the state machine for a protocol utilizing pulldown voltages as a mechanism for device discovery (i.e., by the other device on the link) may be compromised by the presence of a retimer. While some specialized retimers may be developed to address this specific issue, such implementations may be expensive and unavailable. In one example, an additional low power state L1b 705 may be added to the state machine. In this example, an assumption can be made that a receiver detect state 710 will be compromised any time a repeater device is present on a link, as endpoint devices connected to the repeater will detect a pulldown voltage in satisfaction of the receiver detect state 710, but will be unable to discern if that pulldown voltage is evidence of another endpoint being present on the link or if the pulldown voltage is merely a pulldown voltage resulting from the repeater's own terminations. In such instances, the transmitter detect state 715 may take on added importance.

In one example, detect sequences may be defined to be sent by each of the transmitters of the devices (e.g., 1305, 1310) in a transmitter detect state. Should a device receive the expected detect sequence (or other defined signal for the detect state), the receiving device may determine that another endpoint device with a protocol-compatible transmitter is present on the other end of the link. Ordinarily (i.e., when no repeater is present), state machine logic of a device's agent will not proceed to the transmitter detect state 715 unless it has already determined another endpoint to be there (based on satisfaction of the receiver detect state 710). In the case of a repeater being present on the link, it may be that a particular device (through is state machine logic) progresses from the receiver detect state 710 to the transmitter detect state 715 even when no other endpoint device is present on the link (i.e., with only the particular device and repeater present on the link). The particular device may then monitor its receiver for an incoming detect signal, but with no success. Rather than having the particular device determine a deadlock and exit Tx Detect 715 to a reset state (which may be unnecessarily expensive and result in the particular device again unsuccessfully progressing to Tx Detect), the L1b state 705 may be introduced to allow the state machine logic of the particular device to fall into a low power state 705 (i.e., to conserve power) for a period instead of to a reset. For instance, upon reaching the Tx Detect state 715, the particular device may monitor the lanes for a detect signal for a particular duration. If no detect signal is received during this particular duration, clock logic of the particular device may prompt the state machine logic to transition temporarily from the Tx Detect state 715 to the L1b state 705. Here, in L1b 705, all but wake monitoring logic (on one or more lanes) may be powered down on the particular device. The particular device may remain in L1b 705 for another duration of time, before transitioning back to the Tx Detect state 715 to try again, monitoring the link for a detect signal from another endpoint device. In some implementations, the device may continue to switch between the Tx Detect 715 and L1b 705 states until forward progress is made (i.e., through the addition of a corresponding other endpoint device). In some cases, a timeout may be defined such that if a device transitions multiple times between the Tx Detect 715 and L1b 705 over a duration of time without making forward progress (e.g., receiving detect signals from another device), then the device may be sent to a reset state or simply powered off, among other examples.

Turning to FIG. 14, a flowchart 1400 is shown of an example portion of the initialization and training of a particular link. For instance, state machine logic of an agent of a particular device (e.g., an endpoint processor device or node, accelerator, node controller, etc.) may enter a receiver detect state 1405 and monitor a transmitter of the device for a pulldown voltage evidencing that another device is connected to the particular device over the link. The other device may either be another endpoint device or a repeater device, in some examples. A pulldown voltage may be detected 1410 and the state machine logic may exit 1415 the receiver detect state based on the detected pulldown voltage. The state machine logic may transition 1420 to directly to a transmitter detect state or may first transition to and out of one or more intermediate link training states before entering 1420 the transmitter detect state. In the transmitter detect state, a receiver of the particular device may be monitored for the transmission of a signal (e.g., corresponding to the transmitter detect state, such as a Detect supersequence). The particular device may attempt to identify the receipt of such a signal for a time. If a detect signal is not received (at 1425), the state machine logic may transition 1430 to a low power state for a duration, causing the device (or the portion of the device corresponding to the link) to enter a low power mode. After a duration, the state machine logic may re-enter 1420 the transmitter detect state from the low power state to again attempt to detect a signal corresponding to the presence of a compatible transmitter on another endpoint device on the link. If an expected detect signal is received (e.g., 1425) in the transmitter detect state, the state machine logic may cause an exit 1435 from the transmitter detect state to one or more other states defined in a link training state machine (e.g., a polling state), among other examples.

UPI can be incorporated in any variety of computing devices and systems, including mainframes, server systems, personal computers, mobile computers (such as tablets, smartphones, personal digital systems, etc.), smart appliances, gaming or entertainment consoles and set top boxes, among other examples. For instance, referring to FIG. 18, an embodiment of a block diagram for a computing system including a multicore processor is depicted. Processor 1800 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a handheld processor, an application processor, a co-processor, a system on a chip (SOC), or other device to execute code. Processor 1800, in one embodiment, includes at least two cores—core 1801 and 1802, which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, processor 1800 may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.

Physical processor 1500, as illustrated in FIG. 15, includes two cores—core 1501 and 1502. Here, core 1501 and 1502 are considered symmetric cores, i.e. cores with the same configurations, functional units, and/or logic. In another embodiment, core 1501 includes an out-of-order processor core, while core 1502 includes an in-order processor core. However, cores 1501 and 1502 may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated Instruction Set Architecture (ISA), a co-designed core, or other known core. In a heterogeneous core environment (i.e. asymmetric cores), some form of translation, such a binary translation, may be utilized to schedule or execute code on one or both cores. Yet to further the discussion, the functional units illustrated in core 1501 are described in further detail below, as the units in core 1502 operate in a similar manner in the depicted embodiment.

As depicted, core 1501 includes two hardware threads 1501 a and 1501 b, which may also be referred to as hardware thread slots 1501 a and 1501 b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 1500 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1501 a, a second thread is associated with architecture state registers 1501 b, a third thread may be associated with architecture state registers 1502 a, and a fourth thread may be associated with architecture state registers 1502 b. Here, each of the architecture state registers (1501 a, 1501 b, 1502 a, and 1502 b) may be referred to as processing elements, thread slots, or thread units, as described above. As illustrated, architecture state registers 1501 a are replicated in architecture state registers 1501 b, so individual architecture states/contexts are capable of being stored for logical processor 1501 a and logical processor 1501 b. In core 1501, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 1530 may also be replicated for threads 1501 a and 1501 b. Some resources, such as re-order buffers in reorder/retirement unit 1535, ILTB 1520, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 1515, execution unit(s) 1540, and portions of out-of-order unit 1535 are potentially fully shared.

Processor 1500 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In FIG. 15, an embodiment of a purely exemplary processor with illustrative logical units/resources of a processor is illustrated. Note that a processor may include, or omit, any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As illustrated, core 1501 includes a simplified, representative out-of-order (OOO) processor core. But an in-order processor may be utilized in different embodiments. The OOO core includes a branch target buffer 1520 to predict branches to be executed/taken and an instruction-translation buffer (I-TLB) 1520 to store address translation entries for instructions.

Core 1501 further includes decode module 1525 coupled to fetch unit 1520 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1501 a, 1501 b, respectively. Usually core 1501 is associated with a first ISA, which defines/specifies instructions executable on processor 1500. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 1525 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. For example, as discussed in more detail below decoders 1525, in one embodiment, include logic designed or adapted to recognize specific instructions, such as transactional instruction. As a result of the recognition by decoders 1525, the architecture or core 1501 takes specific, predefined actions to perform tasks associated with the appropriate instruction. It is important to note that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note decoders 1526, in one embodiment, recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 1526 recognize a second ISA (either a subset of the first ISA or a distinct ISA).

In one example, allocator and renamer block 1530 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1501 a and 1501 b are potentially capable of out-of-order execution, where allocator and renamer block 1530 also reserves other resources, such as reorder buffers to track instruction results. Unit 1530 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1500. Reorder/retirement unit 1535 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.

Scheduler and execution unit(s) block 1540, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) 1550 are coupled to execution unit(s) 1540. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.

Here, cores 1501 and 1502 share access to higher-level or further-out cache, such as a second level cache associated with on-chip interface 1510. Note that higher-level or further-out refers to cache levels increasing or getting further way from the execution unit(s). In one embodiment, higher-level cache is a last-level data cache—last cache in the memory hierarchy on processor 1500—such as a second or third level data cache. However, higher level cache is not so limited, as it may be associated with or include an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 1525 to store recently decoded traces. Here, an instruction potentially refers to a macro-instruction (i.e. a general instruction recognized by the decoders), which may decode into a number of micro-instructions (micro-operations).

In the depicted configuration, processor 1500 also includes on-chip interface module 1510. Historically, a memory controller, which is described in more detail below, has been included in a computing system external to processor 1500. In this scenario, on-chip interface 1510 is to communicate with devices external to processor 1500, such as system memory 1575, a chipset (often including a memory controller hub to connect to memory 1575 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 1505 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.

Memory 1575 may be dedicated to processor 1500 or shared with other devices in a system. Common examples of types of memory 1575 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1580 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

Recently however, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 1500. For example in one embodiment, a memory controller hub is on the same package and/or die with processor 1500. Here, a portion of the core (an on-core portion) 1510 includes one or more controller(s) for interfacing with other devices such as memory 1575 or a graphics device 1580. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, on-chip interface 1510 includes a ring interconnect for on-chip communication and a high-speed serial point-to-point link 1505 for off-chip communication. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 1575, graphics processor 1580, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.

In one embodiment, processor 1500 is capable of executing a compiler, optimization, and/or translator code 1577 to compile, translate, and/or optimize application code 1576 to support the apparatus and methods described herein or to interface therewith. A compiler often includes a program or set of programs to translate source text/code into target text/code. Usually, compilation of program/application code with a compiler is done in multiple phases and passes to transform hi-level programming language code into low-level machine or assembly language code. Yet, single pass compilers may still be utilized for simple compilation. A compiler may utilize any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

Larger compilers often include multiple phases, but most often these phases are included within two general phases: (1) a front-end, i.e. generally where syntactic processing, semantic processing, and some transformation/optimization may take place, and (2) a back-end, i.e. generally where analysis, transformations, optimizations, and code generation takes place. Some compilers refer to a middle, which illustrates the blurring of delineation between a front-end and back end of a compiler. As a result, reference to insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as any other known phases or passes of a compiler. As an illustrative example, a compiler potentially inserts operations, calls, functions, etc. in one or more phases of compilation, such as insertion of calls/operations in a front-end phase of compilation and then transformation of the calls/operations into lower-level code during a transformation phase. Note that during dynamic compilation, compiler code or dynamic optimization code may insert such operations/calls, as well as optimize the code for execution during runtime. As a specific illustrative example, binary code (already compiled code) may be dynamically optimized during runtime. Here, the program code may include the dynamic optimization code, the binary code, or a combination thereof.

Similar to a compiler, a translator, such as a binary translator, translates code either statically or dynamically to optimize and/or translate code. Therefore, reference to execution of code, application code, program code, or other software environment may refer to: (1) execution of a compiler program(s), optimization code optimizer, or translator either dynamically or statically, to compile program code, to maintain software structures, to perform other operations, to optimize code, or to translate code; (2) execution of main program code including operations/calls, such as application code that has been optimized/compiled; (3) execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software related operations, or to optimize code; or (4) a combination thereof.

Referring now to FIG. 16, shown is a block diagram of an embodiment of a multicore processor. As shown in the embodiment of FIG. 16, processor 1600 includes multiple domains. Specifically, a core domain 1630 includes a plurality of cores 1630A-1630N, a graphics domain 1660 includes one or more graphics engines having a media engine 1665, and a system agent domain 1610.

In various embodiments, system agent domain 1610 handles power control events and power management, such that individual units of domains 1630 and 1660 (e.g. cores and/or graphics engines) are independently controllable to dynamically operate at an appropriate power mode/level (e.g. active, turbo, sleep, hibernate, deep sleep, or other Advanced Configuration Power Interface like state) in light of the activity (or inactivity) occurring in the given unit. Each of domains 1630 and 1660 may operate at different voltage and/or power, and furthermore the individual units within the domains each potentially operate at an independent frequency and voltage. Note that while only shown with three domains, understand the scope of the present disclosure is not limited in this regard and additional domains may be present in other embodiments.

As shown, each core 1630 further includes low level caches in addition to various execution units and additional processing elements. Here, the various cores are coupled to each other and to a shared cache memory that is formed of a plurality of units or slices of a last level cache (LLC) 1640A-1640N; these LLCs often include storage and cache controller functionality and are shared amongst the cores, as well as potentially among the graphics engine too.

As seen, a ring interconnect 1650 couples the cores together, and provides interconnection between the core domain 1630, graphics domain 1660 and system agent circuitry 1610, via a plurality of ring stops 1652A-1652N, each at a coupling between a core and LLC slice. As seen in FIG. 16, interconnect 1650 is used to carry various information, including address information, data information, acknowledgement information, and snoop/invalid information. Although a ring interconnect is illustrated, any known on-die interconnect or fabric may be utilized. As an illustrative example, some of the fabrics discussed above (e.g. another on-die interconnect, On-chip System Fabric (OSF), an Advanced Microcontroller Bus Architecture (AMBA) interconnect, a multi-dimensional mesh fabric, or other known interconnect architecture) may be utilized in a similar fashion.

As further depicted, system agent domain 1610 includes display engine 1612 which is to provide control of and an interface to an associated display. System agent domain 1610 may include other units, such as: an integrated memory controller 1620 that provides for an interface to a system memory (e.g., a DRAM implemented with multiple DIMMs; coherence logic 1622 to perform memory coherence operations. Multiple interfaces may be present to enable interconnection between the processor and other circuitry. For example, in one embodiment at least one direct media interface (DMI) 1616 interface is provided as well as one or more PCIe™ interfaces 1614. The display engine and these interfaces typically couple to memory via a PCIe™ bridge 1618. Still further, to provide for communications between other agents, such as additional processors or other circuitry, one or more other interfaces may be provided.

Referring now to FIG. 17, shown is a block diagram of a second system 1700 in accordance with an embodiment of the present disclosure. As shown in FIG. 17, multiprocessor system 1700 is a point-to-point interconnect system, and includes a first processor 1770 and a second processor 1780 coupled via a point-to-point interconnect 1750. Each of processors 1770 and 1780 may be some version of a processor. In one embodiment, 1752 and 1754 are part of a serial, point-to-point coherent interconnect fabric, such as a high-performance architecture. As a result, the concepts described herein may be implemented within the UPI architecture.

While shown with only two processors 1770, 1780, it is to be understood that the scope of the present disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors 1770 and 1780 are shown including integrated memory controller units 1772 and 1782, respectively. Processor 1770 also includes as part of its bus controller units point-to-point (P-P) interfaces 1776 and 1778; similarly, second processor 1780 includes P-P interfaces 1786 and 1788. Processors 1770, 1780 may exchange information via a point-to-point (P-P) interface 1750 using P-P interface circuits 1778, 1788. As shown in FIG. 17, IMCs 1772 and 1782 couple the processors to respective memories, namely a memory 1732 and a memory 1734, which may be portions of main memory locally attached to the respective processors.

Processors 1770, 1780 each exchange information with a chipset 1790 via individual P-P interfaces 1752, 1754 using point to point interface circuits 1776, 1794, 1786, 1798. Chipset 1790 also exchanges information with a high-performance graphics circuit 1738 via an interface circuit 1792 along a high-performance graphics interconnect 1739.

A shared cache (not shown) may be included in either processor or outside of both processors; yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.

Chipset 1790 may be coupled to a first bus 1716 via an interface 1796. In one embodiment, first bus 1716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the present disclosure is not so limited.

As shown in FIG. 17, various I/O devices 1714 are coupled to first bus 1716, along with a bus bridge 1718 which couples first bus 1716 to a second bus 1720. In one embodiment, second bus 1720 includes a low pin count (LPC) bus. Various devices are coupled to second bus 1720 including, for example, a keyboard and/or mouse 1722, communication devices 1727 and a storage unit 1728 such as a disk drive or other mass storage device which often includes instructions/code and data 1730, in one embodiment. Further, an audio I/O 1724 is shown coupled to second bus 1720. Note that other architectures are possible, where the included components and interconnect architectures vary. For example, instead of the point-to-point architecture of FIG. 17, a system may implement a multi-drop bus or other such architecture.

While the concepts herein have been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present disclosure.

A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language (HDL) or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced at some stages of the design process. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In some implementations, such data may be stored in a database file format such as Graphic Data System II (GDS II), Open Artwork System Interchange Standard (OASIS), or similar format.

In some implementations, software based hardware models, and HDL and other functional description language objects can include register transfer language (RTL) files, among other examples. Such objects can be machine-parsable such that a design tool can accept the HDL object (or model), parse the HDL object for attributes of the described hardware, and determine a physical circuit and/or on-chip layout from the object. The output of the design tool can be used to manufacture the physical device. For instance, a design tool can determine configurations of various hardware and/or firmware elements from the HDL object, such as bus widths, registers (including sizes and types), memory blocks, physical link paths, fabric topologies, among other attributes that would be implemented in order to realize the system modeled in the HDL object. Design tools can include tools for determining the topology and fabric configurations of system on chip (SoC) and other hardware device. In some instances, the HDL object can be used as the basis for developing models and design files that can be used by manufacturing equipment to manufacture the described hardware. Indeed, an HDL object itself can be provided as an input to manufacturing system software to cause the described hardware.

In any representation of the design, the data may be stored in any form of a machine readable medium. A memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present disclosure.

A module as used herein refers to any combination of hardware, software, and/or firmware. As an example, a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the microcontroller to perform predetermined operations. And as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one embodiment, use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

Use of the phrase ‘configured to,’ in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task. In this example, an apparatus or element thereof that is not operating is still ‘configured to’ perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. But a logic gate ‘configured to’ provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term ‘configured to’ does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.

Furthermore, use of the phrases ‘to,’ ‘capable of/to,’ and or ‘operable to,’ in one embodiment, refers to some apparatus, logic, hardware, and/or element designed in such a way to enable use of the apparatus, logic, hardware, and/or element in a specified manner. Note as above that use of to, capable to, or operable to, in one embodiment, refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.

A value, as used herein, includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as 1's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level. In one embodiment, a storage cell, such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values in computer systems have been used. For example the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information capable of being held in a computer system.

Moreover, states may be represented by values or portions of values. As an example, a first value, such as a logical one, may represent a default or initial state, while a second value, such as a logical zero, may represent a non-default state. In addition, the terms reset and set, in one embodiment, refer to a default and an updated value or state, respectively. For example, a default value potentially includes a high logical value, i.e. reset, while an updated value potentially includes a low logical value, i.e. set. Note that any combination of values may be utilized to represent any number of states.

The embodiments of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. A non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc, which are to be distinguished from the non-transitory mediums that may receive information there from.

Instructions used to program logic to perform embodiments of the disclosure may be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

The following examples pertain to embodiments in accordance with this Specification. Example 1 is an apparatus including an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus may further include a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

Example 2 may include the subject matter of example 1, where the multiplexer includes a plurality of two input multiplexers.

Example 3 may include the subject matter of example 2, where each lane in one of the links is connected to two respective multiplexers in the plurality of multiplexers.

Example 4 may include the subject matter of example 3, where the plurality of two input multiplexers includes a number of two-input multiplexers equal to the first number, a first subset of the plurality of two-input multiplexers are to be disabled when in the second mode, and only a second subset of the plurality of multiplexers other than the first subset of multiplexers are to be connected to the second number of lanes when in the second mode.

Example 5 may include the subject matter of example 4, where lanes are to be connected to respective multiplexers in the plurality of multiplexers according to a sequence and the first subset of multiplexers corresponds to a middle of the sequence.

Example 6 may include the subject matter of any one of examples 3-5, where a first one of the two inputs of each of the plurality of multiplexers is connected to a respective lane according to a numbering of the lanes and a second one of the two inputs of each of the plurality of multiplexers is connected to another lane according to a reverse numbering of the lanes.

Example 7 may include the subject matter of any one of examples 1-6, where the first number of lanes includes 24 lanes and the second number of lanes includes 20 lanes.

Example 8 may include the subject matter of any one of examples 1-7, further including protocol logic to send a set of signals on each lane of the particular link, where each signal in the set of signals is at least partially based on the respective lane on which it is to be sent.

Example 9 may include the subject matter of any one of examples 1-8, where one or more of the set of signals include a pseudo random bit sequence-based signal.

Example 10 is an apparatus including a first device that includes a receiver to receive data on a first set of lanes from one or more other devices, a transmitter to transmit data on a second set of lanes to one or more other devices, and state machine logic. The state machine logic may enter a receiver detect state in a state machine, detect another device connected to the second set of lanes when in the receiver detect state, transition to a transmitter detect state in the state machine based at least in part on detection of the other device on the second set of lanes, monitor the first set of lanes for instances of a particular signal when in the transmitter detect state, enter a particular low power state if no instances of the particular signal are received at the receiver over a first duration of time, and transition from the particular low power state back to the transmitter detect state after a second duration of time.

Example 11 may include the subject matter of example 10, where the state machine logic is further to cause the transmitter to send one or more instances of the particular signal on the first set of lanes when in the transmitter detect state.

Example 12 may include the subject matter of any one of examples 10-11, where the particular signal includes a sequence including an electrical ordered set (EOS) followed by a predefined number of training sequences in series.

Example 13 may include the subject matter of example 12, further including an agent to operate in one of at least two modes, where the EOS includes an electrical idle exit ordered set (EIEOS), a first version of the EIEOS is to be used in a first of the two modes and includes a repeating pattern of a first byte with value 0x00 followed by a second byte with 0xFFFF, and a second version of the EIEOS is to be used in a second of the two modes and includes a repeating pattern of first and second bytes with value 0x00 followed by third and fourth bytes with 0xFFFF.

Example 14 may include the subject matter of any one of examples 12-13, where the number of training sequences indicates the transmitter detect state.

Example 15 may include the subject matter of any one of examples 10-14, where the state machine logic is further to identify a particular instance of the particular signal received by the receiver in the transmitter detect state, and transition to another state based at least in part on receipt of the particular instance of the particular signal.

Example 16 may include the subject matter of any one of examples 10-15, where detecting the other device connected to the second set of lanes in the receiver detect state includes detecting a pull down voltage on the second set of lanes.

Example 17 may include the subject matter of example 16, where the pull down voltage is generated from a repeater device connected on the second set of lanes and instances of the particular signal indicate presence of a second device connected to the first device over the repeater device.

Example 18 may include the subject matter of example 17, further including the repeater device and second device.

Example 19 may include the subject matter of any one of examples 10-18, further including wake monitoring logic to detect wake signals, where the wake monitoring logic is to remain on during the particular low power state.

Example 20 is a system including a first device and a second device connected to the first device by an interconnect including a plurality of lanes, where the second device includes an agent to facilitate communication on the interconnect in one of two or more modes, communications are to be over links with a first number of lanes in a first one of the two or more modes, communications are to be over links with a second number of lanes in a second one of the two or more modes, and the agent includes state machine logic to detect another device connected on the interconnect when in a receiver detect state of a state machine, transition to a transmitter detect state in the state machine based at least in part on detection of the other device in the receiver detect state, monitor the first set of lanes for instances of a particular signal when in the transmitter detect state, and temporarily exit the transmitter detect to a particular low power state if no instances of the particular signal are received over a particular duration of time in the transmitter detect state, where the second device further includes a multiplexer to reverse lanes in either one of the first or second modes.

Example 21 may include the subject matter of example 20, wherein the agent further comprises adaptation logic to participate in adaptation of a first direction of the link and participate in adaptation of a second direction of the link following completion of the adaptation of the first direction of the link.

Example 22 may include the subject matter of any one of examples 20-21, wherein the first number of lanes comprises 24 lanes and the second number of lanes comprises 20 lane modes.

Example 23 may include the subject matter of any one of examples 20-22, wherein the particular signal comprises a sequence comprising an electrical ordered set (EOS) followed by a predefined number of training sequences in series.

Example 24 may include the subject matter of example 21, wherein the EOS comprises an electrical idle exit ordered set (EIEOS), a first version of the EIEOS is to be used in a first of the two modes and comprises a repeating pattern of a first byte with value 0x00 followed by a second byte with 0xFFFF, and a second version of the EIEOS is to be used in a second of the two modes and comprises a repeating pattern of first and second bytes with value 0x00 followed by third and fourth bytes with 0xFFFF.

Example 25 may include the subject matter of any one of examples 20-24, wherein the first device comprises an accelerator.

Example 26 may include the subject matter of any one of examples 20-24, wherein the first device comprises a processor device.

Example 27 may include the subject matter of any one of examples 20-24, wherein the first device comprises a node controller.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Furthermore, the foregoing use of embodiment and other exemplarily language does not necessarily refer to the same embodiment or the same example, but may refer to different and distinct embodiments, as well as potentially the same embodiment. 

What is claimed is:
 1. An apparatus comprising: an agent to facilitate communication in one of two or more modes, wherein a first of the two or more modes involves communication over links comprising a first number of lanes and a second of the two or more modes involves communication over links comprising a second number of lanes, and the first number is greater than the second number; a memory comprising data to indicate which of the two or modes applies to a particular link; and a multiplexer to reverse lane numbering on links comprising either the first number of lanes or the second number of lanes.
 2. The apparatus of claim 1, wherein the multiplexer comprises a plurality of two input multiplexers.
 3. The apparatus of claim 2, wherein each lane in one of the links is connected to two respective multiplexers in the plurality of multiplexers.
 4. The apparatus of claim 3, wherein the plurality of two input multiplexers comprises a number of two-input multiplexers equal to the first number, a first subset of the plurality of two-input multiplexers are to be disabled when in the second mode, and only a second subset of the plurality of multiplexers other than the first subset of multiplexers are to be connected to the second number of lanes when in the second mode.
 5. The apparatus of claim 4, wherein lanes are to be connected to respective multiplexers in the plurality of multiplexers according to a sequence and the first subset of multiplexers corresponds to a middle of the sequence.
 6. The apparatus of claim 3, wherein a first one of the two inputs of each of the plurality of multiplexers is connected to a respective lane according to a numbering of the lanes and a second one of the two inputs of each of the plurality of multiplexers is connected to another lane according to a reverse numbering of the lanes.
 7. The apparatus of claim 1, wherein the first number of lanes comprises 24 lanes and the second number of lanes comprises 20 lanes.
 8. The apparatus of claim 1, further comprising protocol logic to send a set of signals on each lane of the particular link, wherein each signal in the set of signals is at least partially based on the respective lane on which it is to be sent.
 9. The apparatus of claim 1, wherein one or more of the set of signals comprise a pseudo random bit sequence-based signal.
 10. An apparatus comprising: a first device comprising: a receiver to receive data on a first set of lanes from one or more other devices; a transmitter to transmit data on a second set of lanes to one or more other devices; and state machine logic to: enter a receiver detect state in a state machine; detect another device connected to the second set of lanes when in the receiver detect state; transition to a transmitter detect state in the state machine based at least in part on detection of the other device on the second set of lanes; monitor the first set of lanes for instances of a particular signal when in the transmitter detect state; enter a particular low power state if no instances of the particular signal are received at the receiver over a first duration of time; and transition from the particular low power state back to the transmitter detect state after a second duration of time.
 11. The apparatus of claim 10, wherein the state machine logic is further to cause the transmitter to send one or more instances of the particular signal on the first set of lanes when in the transmitter detect state.
 12. The apparatus of claim 10, wherein the particular signal comprises a sequence comprising an electrical ordered set (EOS) followed by a predefined number of training sequences in series.
 13. The apparatus of claim 12, further comprising an agent to operate in one of at least two modes, wherein the EOS comprises an electrical idle exit ordered set (EIEOS), a first version of the EIEOS is to be used in a first of the two modes and comprises a repeating pattern of a first byte with value 0x00 followed by a second byte with 0xFFFF, and a second version of the EIEOS is to be used in a second of the two modes and comprises a repeating pattern of first and second bytes with value 0x00 followed by third and fourth bytes with 0xFFFF.
 14. The apparatus of claim 12, wherein the number of training sequences indicates the transmitter detect state.
 15. The apparatus of claim 10, wherein the state machine logic is further to: identify a particular instance of the particular signal received by the receiver in the transmitter detect state; and transition to another state based at least in part on receipt of the particular instance of the particular signal.
 16. The apparatus of claim 10, wherein detecting the other device connected to the second set of lanes in the receiver detect state comprises detecting a pull down voltage on the second set of lanes.
 17. The apparatus of claim 16, wherein the pull down voltage is generated from a repeater device connected on the second set of lanes and instances of the particular signal indicate presence of a second device connected to the first device over the repeater device.
 18. The apparatus of claim 17, further comprising the repeater device and second device.
 19. The apparatus of claim 10, further comprising wake monitoring logic to detect wake signals, wherein the wake monitoring logic is to remain on during the particular low power state.
 20. A system comprising: a first device; a second device connected to the first device by an interconnect comprising a plurality of lanes, wherein the second device comprises an agent to facilitate communication on the interconnect in one of two or more modes, communications are to be over links with a first number of lanes in a first one of the two or more modes, communications are to be over links with a second number of lanes in a second one of the two or more modes, and the agent comprises: state machine logic to: detect another device connected on the interconnect when in a receiver detect state of a state machine; transition to a transmitter detect state in the state machine based at least in part on detection of the other device in the receiver detect state; monitor the first set of lanes for instances of a particular signal when in the transmitter detect state; and temporarily exit the transmitter detect to a particular low power state if no instances of the particular signal are received over a particular duration of time in the transmitter detect state; wherein the second device further comprises a multiplexer to reverse lanes in either one of the first or second modes. 